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| STPC(R) ATLAS X86 Core PC Compatible System-on-Chip for Terminals s s s POWERFUL x86 PROCESSOR 64-BIT SDRAM UMA CONTROLLER GRAPHICS CONTROLLER - VGA & SVGA CRT CONTROLLER - 135MHz RAMDAC - ENHANCED 2D GRAPHICS ENGINE VIDEO INPUT PORT VIDEO PIPELINE - UP-SCALER - VIDEO COLOUR SPACE CONVERTER - CHROMA & COLOUR KEY SUPPORT TFT DISPLAY CONTROLLER PCI 2.1 MASTER / SLAVE / ARBITER ISA MASTER / SLAVE CONTROLLER 16-BIT LOCAL BUS INTERFACE PCMCIA INTERFACE CONTROLLER EIDE CONTROLLER 2 USB HOST HUB INTERFACES I/O FEATURES - PC/AT+ KEYBOARD CONTROLLER - PS/2 MOUSE CONTROLLER - 2 SERIAL PORTS - 1 PARALLEL PORT - 16 GENERAL PURPOSE I/Os - IC INTERFACE INTEGRATED PERIPHERAL CONTROLLER - DMA CONTROLLER - INTERRUPT CONTROLLER - TIMER / COUNTERS POWER MANAGEMENT UNIT WATCHDOG JTAG IEEE1149.1 SVGA CRTC ST PC At s s las PBGA516 s s s s s s s s Figure 0-1. Logic Diagram Host I/F x86 Core PCI m/s PCI Bus USB PMU wdog IPC ISA m/s PCI m/s I/Os IDE I/F ISA Bus PCMCIA s LB ctrl Local Bus Video Pipeline s s s C Key K Key LUT Monitor Cursor GE I/F VIP SDRAM CTRL TFT I/F TFT Video In Issue 1.0 - July 24, 2002 1/111 STPC(R) ATLAS DESCRIPTION The STPC Atlas integrates a standard 5th generation x86 core along with a powerful UMA graphics/video chipset, support logic including PCI, ISA, Local Bus, USB, EIDE controllers and combines them with standard I/O interfaces to provide a single PC compatible subsystem on a single device, suitable for all kinds of terminal and industrial appliances. s s s s s s s s s s s s s s s s s s s s s s s s s s s s s X86 Processor core Fully static 32-bit 5-stage pipeline, x86 processor fully PC compatible. Can access up to 4GB of external memory. 8Kbyte unified instruction and data cache with write back and write through capability. Parallel processing integral floating point unit, with automatic power down. Runs up to 133 MHz (X2). Fully static design for dynamic clock control. Low power and system management modes. Optimized design for 2.5V operation. SDRAM Controller 64-bit data bus. Up to 90MHz SDRAM clock speed. Integrated system memory, graphic frame memory and video frame memory. Supports 8MB up to 128 MB system memory. Supports 16-Mbit, 64-Mbit and 128-Mbit SDRAMs. Supports 8, 16, 32, 64, and 128 MB DIMMs. Supports buffered, non buffered, and registered DIMMs 4-line write buffers for CPU to DRAM and PCI to DRAM cycles. 4-line read prefetch buffers for PCI masters. Programmable latency Programmable timing for SDRAM parameters. Supports -8, -10, -12, -13, -15 memory parts Supports memory hole between 1MB and 8MB for PCI/ISA busses. 32-bit access, Autoprecharge & Power-down are not supported. s s s s Enhanced 2D Graphics Controller Supports pixel depths of 8, 16, 24 and 32 bit. Full BitBLT implementation for all 256 raster operations defined for Windows. Supports 4 transparent BLT modes - Bitmap Transparency, Pattern Transparency, Source Transparency and Destination Transparency. Hardware clipping Fast line draw engine with anti-aliasing. Supports 4-bit alpha blended font for antialiased text display. Complete double buffered registers for pipelined operation. 64-bit wide pipelined architecture running at 90 MHz. Hardware clipping CRT Controller Integrated 135MHz triple RAMDAC allowing for 1280 x 1024 x 75Hz display. 8-, 16-, 24-bit pixels. Interlaced or non-interlaced output. Video Input port Accepts video inputs in CCIR 601/656 mode. Optional 2:1 decimator Stores captured video in off setting area of the onboard frame buffer. HSYNC and B/T generation or lock onto external video timing source. Video Pipeline Two-tap interpolative horizontal filter. Two-tap interpolative vertical filter. Color space conversion (RGB to YUV and YUV to RGB). Programmable window size. Chroma and color keying for integrated video overlay. s s s s s s s s s s s s s s s 2/111 Issue 1.0 - July 24, 2002 STPC(R) ATLAS s s s s s s s s s TFT Interface Programmable panel size up to 1024 by 1024 pixels. Support for VGA and SVGA active matrix TFT flat panels with 9, 12, 18-bit interface (1 pixel per clock). Support for XGA and SXGA active matrix TFT flat panels with 2 x 9-bit interface (2 pixels per clock). Programmable image positionning. Programmable blank space insertion in text mode. Programmable horizontal and vertical image expansion in graphic mode. One fully programmable PWM (Pulse Width Modulator) signals to adjust the flat panel brightness and contrast. Supports PanelLinkTM high speed serial transmitter externally for high resolution panel interface. PCI Controller Compatible with PCI 2.1 specification. Integrated PCI arbitration interface. Up to 3 masters can connect directly. External logic allows for greater than 3 masters. Translation of PCI cycles to ISA bus. Translation of ISA master initiated cycle to PCI. Support for burst read/write from PCI master. PCI clock is 1/2, 1/3 or 1/4 Host bus clock. ISA master/slave Generates the ISA clock from either 14.318MHz oscillator clock or PCI clock Supports programmable extra wait state for ISA cycles Supports I/O recovery time for back to back I/O cycles. Fast Gate A20 and Fast reset. Supports the single ROM that C, D, or E. blocks shares with F block BIOS ROM. Supports flash ROM. Supports ISA hidden refresh. Buffered DMA & ISA master cycles to reduce bandwidth utilization of the PCI and Host bus. s s s s s s s s s s s s s s s s s Local Bus interface Multiplexed with ISA/DMA interface. Low latency asynchronous bus 16-bit data bus with word steering capability. Programmable timing (Host clock granularity) 4 Programmable Flash Chip Select. 8 Programmable I/O Chip Select. I/O device timing (setup & recovery time) programmable Supports 32-bit Flash burst. 2-level hardware key protection for Flash boot block protection. Supports 2 banks of 32MB flash devices with boot block shadowed to 0x000F0000. Reallocatable Memory space Windows EIDE Interface Supports PIO Transfer Rates to 22 MBytes/sec Supports up to 4 IDE devices Concurrent channel operation (PIO modes) 4 x 32-Bit Buffer FIFOs per channel Support for PIO mode 3 & 4. Individual drive timing for all four IDE devices Supports both legacy & native IDE modes Supports hard drives larger than 528MB Support for CD-ROM and tape peripherals Backward compatibility with IDE (ATA-1). Integrated Peripheral Controller 2X8237/AT compatible 7-channel DMA controller. 2X8259/AT compatible interrupt Controller. 16 interrupt inputs - ISA and PCI. Three 8254 compatible Timer/Counters. Co-processor error support logic. Supports external RTC (Not in Local Bus Mode). s s s s s s s s s s s s s s s s s s s s s s s s s s s s Issue 1.0 - July 24, 2002 3/111 STPC(R) ATLAS s s s s s PCMCIA interface Support one PCMCIA 68-pin standard PC Card Socket. Power Management support. Support PCMCIA/ATA specifications. Support I/O PC Card with pulse-mode interrupts. USB Interface USB 1.1 compatible. Open HCI 1.0 compliant. User configurable RootHub. Support for both LowSpeed and HighSpeed USB devices. No bi-directionnal or Tri-state busses. No level sensitive latches. System Management Interrupt pin support Hooks for legacy device support. Keyboard interface Fully PC/AT+ compatible Mouse interface Fully PS/2 compatible Serial interface 15540 compatible Programmable word length, stop bits, parity. 16-bit programmable baud rate generator. Interrupt generator. Loop-back mode. 8-bit scratch register. Two 16-bit FIFOs. Two DMA handshake lines. s s Parallel port All IEEE Standard 1284 protocols supported: Compatibility, Nibble, Byte, EPP, and ECP modes. 16 bytes FIFO for ECP. Power Management Four power saving modes: On, Doze, Standby, Suspend. Programmable system activity detector Supports Intel & Cyrix SMM and APM. Supports STOPCLK. Supports IO trap & restart. Independent peripheral time-out timer to monitor hard disk, serial & parallel port. 128K SM_RAM address space from 0xA0000 to 0xB0000 JTAG Boundary Scan compatible IEEE1149.1. Scan Chain control. Bypass register compatible IEEE1149.1. ID register compatible IEEE1149.1. RAM BIST control. s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s . ExCA is a trademark of PCMCIA / JEIDA. PanelLink is a trademark of SiliconImage, Inc 4/111 Issue 1.0 - July 24, 2002 GENERAL DESCRIPTION 1. GENERAL DESCRIPTION At the heart of the STPC Atlas is an advanced processor block that includes a powerful x86 processor core along with a 64-bit SDRAM controller, advanced 64-bit accelerated graphics and video controller, a high speed PCI bus controller and industry standard PC chip set functions (Interrupt controller, DMA Controller, Interval timer and ISA bus). The STPC Atlas has in addition, a TFT output, a Video Input, an EIDE controller, a Local Bus interface, PCMCIA and super I/O features including USB host hub. 1.1. ARCHITECTURE The STPC Atlas makes use of a tightly coupled Unified Memory Architecture (UMA), where the same memory array is used for CPU main memory and graphics frame-buffer. This means a reduction in total system memory for system performances that are equal to that of a comparable frame buffer and system memory based system, and generally much better, due to the higher memory bandwidth allowed by attaching the graphics engine directly to the 64-bit processor host interface running at the speed of the processor bus rather than the traditional PCI bus. The 64-bit wide memory array provides the system with an 800MB/s peak bandwidth. This allows for higher resolution screens and greater color depth. The processor bus runs at 133 MHz, further increasing "standard" bandwidth by at least a factor of two. The `standard' PC chipset functions (DMA, interrupt controller, timers, power management logic) are integrated together with the x86 processor core; additional low bandwidth functions such as communication ports are accessed by the STPC Atlas via an internal ISA bus. The PCI bus is the main data communication link to the STPC Atlas chip. The STPC Atlas translates appropriate host bus I/O and Memory cycles onto the PCI bus. It also supports the generation of Configuration cycles on the PCI bus. The STPC Atlas, as a PCI bus agent (host bridge class), is compatible with PCI specification 2.1. The chipset also implements the PCI mandatory header registers in Type 0 PCI configuration space for easy porting of PCI aware system BIOS. The device contains a PCI arbitration function for three external PCI devices. Figure 1-1 describes this architecture. 1.2. GRAPHICS FEATURES Graphics functions are controlled through the onchip SVGA controller and the monitor display is produced through the 2D graphics display engine. This Graphics Engine is tuned to work with the host CPU to provide a balanced graphics system with a low silicon area cost. It performs limited graphics drawing operations which include hardware acceleration of text, bitblts, transparent blts and fills. The results of these operations change the contents of the on-screen or offscreen frame buffer areas of SDRAM memory. The frame buffer can occupy a space up to 4 Mbytes anywhere in the physical main memory. The maximum graphics resolution supported is 1280 x 1024 in 16 Million colours at 75 Hz refresh rate and is VGA and SVGA compatible. Horizontal timing fields are VGA compatible while the vertical fields are extended by one bit to accommodate above display resolution. To generate the TFT output, the STPC Atlas extracts the digital video stream before the RAMDAC and reformats it to the TFT format. The height and width of the flat panel are programmable. 1.3. INTERFACES An industry standard EIDE (ATA 2) controller is built in to the STPC Atlas and connected internally via the PCI bus. The STPC Atlas integrates two USB ports. Universal Serial Bus (USB) is a general purpose communications interface for connecting peripherals to a PC. The USB Open Host Controller Interface (Open HCI) Specification, revision 1.1, supports speeds of up to 12 MB/s. USB is royalty free and is likely to replace lowspeed legacy serial, parallel, keyboard, mouse and floppy drive interfaces. USB Revision 1.1 is fully supported under Microsoft Windows 98 and Windows 2000. The STPC Atlas PCMCIA controller has been specifically designed to provide the interface with PCMCIA cards which contain additional memory or I/O The power management control facilities include socket power control, insertion/removal capability, power saving with Windows inactivity, NCS controlled Chip Power Down, together with further controls for 3.3V suspend with Modem Ring Resume Detection. Issue 1.0 - July 24, 2002 5/111 GENERAL DESCRIPTION The STPC Atlas implements a multi-function parallel port. The standard PC/AT compatible logical address assignments for LPT1, LPT2 and LPT3 are supported. It can be configured for any of the following three modes and supports the IEEE Standard 1284 parallel interface protocol standards, as follows: - Compatibility Mode (Forward channel, standard) - Nibble Mode (Reverse channel, PC compatible) - Byte Mode (Reverse channel, PS/2 compatible) The General Purpose Input/Output (GPIO) interface provides a 16-bit I/O facility, using 16 dedicated device pins. It is organised using two blocks of 8-bit Registers, one for lines 0 to 7, the other for lines 8 to 15. Each GPIO port can be configured as an input or an output simply by programming the associated port direction control register. All GPIO ports are configured as inputs at reset, which also latches the input levels into the Strap Registers. The input states of the ports are thus recorded automatically at reset, and this can be used as a strap register anywhere in the system. 1.4. FEATURE MULTIPLEXING The STPC Atlas BGA package has 516 balls. This however is not sufficient for all of the integrated functions available; some features therefore share the same balls and cannot thus be used at the same time. The STPC Atlas configuration is done by `strap options'. This is a set of pull-up or pulldown resistors on the memory data bus, checked on reset, which auto-configure the STPC Atlas. There 3 multiplexed functions are the external ISA bus, the Local Bus and the PCMCIA interface. 1.5. POWER MANAGEMENT The STPC Atlas core is compliant with the Advanced Power Management (APM) specification to provide a standard method by which the BIOS can control the power used by personal computers. The Power Management Unit (PMU) module controls the power consumption, providing a comprehensive set of features that controls the power usage and supports compliance with the United States Environmental Protection Agency's Energy Star Computer Program. The PMU provides the following hardware structures to assist the software in managing the system power consumption: - System Activity Detection. - 3 power-down timers detecting system inactivity: - Doze timer (short durations). - Stand-by timer (medium durations). - Suspend timer (long durations). - House-keeping activity detection. - House-keeping timer to cope with short bursts of house-keeping activity while dozing or in stand-by state. - Peripheral activity detection. - Peripheral timer detecting peripheral inactivity - SUSP# modulation to adjust the system performance in various power down states of the system including full power-on state. - Power control outputs to disable power from different planes of the board. Lack of system activity for progressively longer periods of time is detected by the three power down timers. These timers can generate SMI interrupts to CPU so that the SMM software can put the system in decreasing states of power consumption. Alternatively, system activity in a power down state can generate an SMI interrupt to allow the software to bring the system back up to full power-on state. The chip-set supports up to three power down states described above; these correspond to decreasing levels of power savings. Power down puts the STPC Atlas into suspend mode. The processor completes execution of the current instruction, any pending decoded instructions and associated bus cycles. During the suspend mode, internal clocks are stopped. Removing power-down, the processor resumes instruction fetching and begins execution in the instruction stream at the point it had stopped. Because of the static nature of the core, no internal data is lost. 1.6. JTAG JTAG stands for Joint Test Action Group and is the popular name for IEEE Std. 1149.1, Standard Test Access Port and Boundary-Scan Architecture. This built-in circuitry is used to assist in the test, maintenance and support of functional circuit blocks. The circuitry includes a standard interface through which instructions and test data are communicated. A set of test features is defined, including a boundary-scan register so that a component is able to respond to a minimum set of test instructions. 6/111 Issue 1.0 - July 24, 2002 GENERAL DESCRIPTION Figure 1-1. Functional description. Host I/F x86 Core USB PCI m/s PCI Bus PMU I/Os IPC ISA m/s PCI m/s IDE I/F ISA Bus PCMCIA LB CTRL Local Bus Video Pipeline C Key K Key LUT SVGA CRTC Monitor Cursor GE I/F VIP TFT I/F TFT Video In SDRAM CTRL JTAG Issue 1.0 - July 24, 2002 7/111 GENERAL DESCRIPTION 1.7. CLOCK TREE The speed of the PLLs is either fixed (DEVCLK), either programmable by strap option (HCLK) either programmable by software (DCLK, MCLK). When in synchronized mode, MCLK speed is fixed to HCLKO speed and HCLKI is generated from MCLKI. The STPC Atlas integrates many features and generates all its clocks from a single 14MHz oscillator. This results in multiple clock domains as described in Figure 1-2. Figure 1-2. STPC Atlas clock architecture MCLKO VCLK DCLK MCLKI VIP CRTC,Video,TFT SDRAM controller GE, LDE, AFE 48MHz DEVCLK PLL DCLK PLL MCLK PLL HCLK PLL HCLKO 1/6 1/26 UARTs ISA PCMCIA IPC USB Kbd/Mouse South Bridge CPU HCLKI x2 North Bridge Host Local Bus PWM 1/4 1/2 // Port 1/2 1/3 1/2 1/4 DEVCLK (24MHz) XTALO XTALI OSC14M (14MHz) ISACLK PCICLKI HCLK PCICLKO 14.31818 MHz 8/111 Issue 1.0 - July 24, 2002 GENERAL DESCRIPTION Figure 1-3. Typical ISA-based Application. RTC 5V tolerant Flash Boot EIDE USB ISA ROMCS# IRQ DMA.ACK DMA.REQ SVGA TFT 2 Serial Ports STPC Atlas Keyboard Parallel Port Mouse VIP 16 GPIOs PCI SDRAM Issue 1.0 - July 24, 2002 9/111 GENERAL DESCRIPTION Figure 1-4. Typical PCMCIA-based Application. 5V tolerant Flash Boot EIDE USB PCMCIA ROMCS# SVGA TFT 2 Serial Ports STPC Atlas Keyboard Parallel Port Mouse VIP 16 GPIOs PCI SDRAM 10/111 Issue 1.0 - July 24, 2002 GENERAL DESCRIPTION Figure 1-5. Typical Local-Bus-based Application. RTC Flash Boot EIDE USB Local Bus IRQ SVGA TFT 2 Serial Ports STPC Atlas Keyboard Parallel Port Mouse VIP 16 GPIOs PCI SDRAM Issue 1.0 - July 24, 2002 11/111 GENERAL DESCRIPTION 12/111 Issue 1.0 - July 24, 2002 PIN DESCRIPTION 2. PIN DESCRIPTION 2.1. INTRODUCTION The STPC Atlas integrates most of the functionalities of the PC architecture. Therefore, many of the traditional interconnections between the host PC microprocessor and the peripheral devices are totally internal to the STPC Atlas. This offers improved performance due to the tight coupling of the processor core and it's peripherals. As a result many of the external pin connections are made directly to the on-chip peripheral functions. Table 2-1 describes the physical implementation listing signal types and their functionalities. Table 2-2 provides a full pin listing and description. Table 2-6 provides a full listing of the STPC Atlas package pin location physical connection. Please refer to the pin allocation drawing for reference. Due to the number of pins available for the package, and the number of functional I/Os, some pins have several functions, selectable by strap option on Reset. Table 2-4 provides a summary of these pins and their functions. Non multi-functional pins associated with a particular function are not available for use elsewhere when that function is disabled. For example, when in the ISA mode, the Local Bus is disabled totally and Local Bus pins are set to the tri-state (high-impedance) condition. Table 2-1. Signal Description Group name Basic Clocks, Reset & Xtal (SYS) SDRAM Controller (SDRAM) PCI Controller ISA Controller Local Bus I/F PCMCIA Controller IDE Controller VGA Controller (VGA) / I2C Video Input Port TFT output USB Controller Serial Interface Keyboard/Mouse Controller Parallel Port GPIO Signals JTAG Signals Miscellaneous Grounds VDD 3.3 V/2.5 V Reserved Total Pin Count Qty 19 95 51 80 67 62 34 100 10 11 24 6 16 4 18 16 5 5 96 36 4 516 Issue 1.0 - July 24, 2002 13/111 PIN DESCRIPTION Table 2-2. Definition of Signal Pins Signal Name Dir Buffer Type1 BASIC CLOCKS AND RESETS SYSRSTI# I SCHMITT_FT SYSRSTO# O BD8STRP_FT XTALI XTALO PCI_CLKI PCI_CLKO ISA_CLK, ISA_CLK2X OSC14M HCLK DEV_CLK DCLK VDD_xxx_PLL I OSCI13B Description System Reset / Power good Reset Output to System 14.31818 MHz Crystal Input External Oscillator Input 14.31818 MHz Crystal Output 33 MHz PCI Input Clock 33 MHz PCI Output Clock ISA Clock x1 and x2 Multiplexer Select Line for IPC ISA bus synchronisation clock 66 MHz Host Clock (Test pin) 24 MHz Peripheral Clock 135 MHz Dot Clock 2.5V Power Supply for PLL Clocks Qty 1 1 1 1 1 1 2 1 1 1 1 7 O I TLCHT_FT O BT8TRP_TC O BT8TRP_TC O I/O O I/O BD8STRP_FT BD4STRP_FT BT8TRP_TC BD4STRP_FT MEMORY CONTROLLER MCLKI I TLCHT_TC MCLKO O BT8TRP_TC CS#[1:0] O BD8STRP_TC CS#[3]/MA[12]/BA[1] CS#[2]/MA[11] MA[10:0] BA[0] RAS#[1:0] CAS#[1:0] MWE# MD[0] MD[53:1] MD[63:54] DQM[7:0] PCI INTERFACE AD[31:0] CBE[3:0] FRAME# TRDY# IRDY# STOP# DEVSEL# PAR PERR# SERR# LOCK# PCI_REQ#[2:0] PCI_GNT#[2:0] PCI_INT#[3:0] O BD16STARUQP_TC O BD16STARUQP_TC O O O O O I/O I/O I/O O BD16STARUQP_TC BD16STARUQP_TC BD16STARUQP_TC BD16STARUQP_TC BD16STARUQP_TC BD8STRUP_FT BD8TRP_TC BD8STRUP_FT BD8STRP_TC Memory Clock Input Memory Clock Output DIMM Chip Select DIMM Chip Select Memory Address Bank Address DIMM Chip Select Memory Address Memory Row & Column Address Bank Address Row Address Strobe Column Address Strobe Write Enable Memory Data Memory Data Memory Data Data Input/Ouput Mask 1 1 2 1 1 11 1 2 2 1 1 53 10 8 I/O I/O I/O I/O I/O I/O I/O I/O I/O O I I O I BD8PCIARP_FT BD8PCIARP_FT BD8PCIARP_FT BD8PCIARP_FT BD8PCIARP_FT BD8PCIARP_FT BD8PCIARP_FT BD8PCIARP_FT BD8PCIARP_FT BD8PCIARP_FT TLCHT_FT BD8PCIARP_FT BD8PCIARP_FT BD4STRUP_FT Address / Data Bus Commands / Byte Enables Cycle Frame Target Ready Initiator Ready Stop Transaction Device Select Parity Signal Transactions Parity Error System Error PCI Lock PCI Request PCI Grant PCI Interrupt Request 32 4 1 1 1 1 1 1 1 1 1 3 3 4 Note1; See Table 2-3 for buffer type descriptions 14/111 Issue 1.0 - July 24, 2002 PIN DESCRIPTION Table 2-2. Definition of Signal Pins Signal Name Dir ISA BUS INTERFACE LA[23:17] O SA[19:0] O SD[15:0] I/O IOCHRDY I ALE O BHE# O MEMR#, MEMW# I/O SMEMR#, SMEMW# O IOR#, IOW# I/O MASTER# I MCS16# I IOCS16# I REF# I AEN O IOCHCK# I RTCRW# O RTCDS# O RTCAS O RMRTCCS# O GPIOCS# I/O IRQ_MUX[3:0] I DACK_ENC[2:0] O DREQ_MUX[1:0] I TC O ISAOE# I KBCS# I/O ZWS# I PCMCIA INTERFACE RESET A[23:0] D[15:0] IORD#, IOWR# WP / IOIS16# BVD2, BVD1 READY# / IREQ# WAIT# OE# WE# REG# CD2#, CD1# CE2#, CE1# VCC5_EN VCC3_EN VPP_PGM VPP_VCC GPI# Buffer Type1 BD8STRUP_FT BD8STRUP_FT BD8STRP_FT BD8STRUP_FT BD4STRP_FT BD8STRUP_FT BD8STRUP_FT BD8STRP_FT BD8STRUP_FT BD4STRUP_FT BD4STRUP_FT BD4STRUP_FT BD8STRP_FT BD8STRUP_FT BD4STRUP_FT BD4STRP_FT BD4STRP_FT BD4STRP_FT BD4STRP_FT BD4STRP_FT BD4STRP_FT BD4STRP_FT BD4STRP_FT BD4STRP_FT BD4STRP_FT BD4STRP_FT BD4STRP_FT Description Unlatched Address Bus Latched Address Bus Data Bus I/O Channel Ready Address Latch Enable System Bus High Enable Memory Read & Write System Memory Read and Write I/O Read and Write Add On Card Owns Bus Memory Chip Select 16 I/O Chip Select 16 Refresh Cycle Address Enable I/O Channel Check (ISA) RTC Read / Write# RTC Data Strobe RTC Address Strobe ROM / RTC Chip Select General Purpose Chip Select Multiplexed Interrupt Request DMA Acknowledge Multiplexed DMA Request ISA Terminal Count ISA (0) / IDE (1) SELECTION External Keyboard CHIP SELECT ZERO WAIT STATE Qty 7 20 16 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 4 3 2 1 1 1 1 O O I/O O I I I I O O O I O O O O O I BD8STRP_FT BD8STRUP_FT BD8STRP_FT BD8STRUP_FT BD4STRUP_FT BD4STRUP_FT BD4STRUP_FT BD8STRUP_FT BD8STRUP_FT BD4STRP_FT BD4STRUP_FT BD4STRUP_FT BD4STRP_FT BD4STRP_FT BD8STRP_FT BD8STRP_FT BD4STRP_FT BD4STRP_FT Reset Address Bus Data Bus I/O Read and Write DMA Request // Write Protect I/O Size is 16 bit Battery Voltage Detect Busy / Ready# // Interrupt Request Wait Output Enable // DMA Terminal Count Write Enable // DMA Terminal Count DMA Acknowledge // Register Card Detect Card Enable Power Switch control: 5 V power Power Switch control: 3.3 V power Power Switch control: Program power Power Switch control: VCC power General Purpose Input 1 24 16 2 1 2 1 1 1 1 1 2 2 1 1 1 1 1 Note1; See Table 2-3 for buffer type descriptions Issue 1.0 - July 24, 2002 15/111 PIN DESCRIPTION Table 2-2. Definition of Signal Pins Signal Name Dir LOCAL BUS INTERFACE PA[24:20,15,9:8,3:0] O PA[19,11] O PA[18:16,14:12,7:4] O PA[10] O PD[15:0] I/O PRD# O PWR# O PRDY I IOCS#[7:4] O IOCS#[3] O IOCS#[2:0] O PBE#[1] O PBE#[0] O FCS0# O FCS1# O FCS_0H# O FCS_0L# O FCS_1H# O FCS_1L# O I/O IRQ_MUX[3:0]1 IDE CONTROLLER DD[15:12] DD[11:0] DA[2:0] PCS1, PCS3 SCS1, SCS3 DIORDY PIRQ/SIRQ PDRQ/SDRQ PDACK#/SDACK# PDIOR#/SDIOR# PDIOW#/SDIOW# Buffer Type1 BD4STRP_FT BD8STRP_FT BD8STRUP_FT BD4STRUP_FT BD8STRP_FT BD4STRUP_FT BD4STRUP_FT BD8STRUP_FT BD4STRUP_FT BD4STRP_FT BD8STRUP_FT BD8STRP_FT BD4STRUP_FT BD4STRP_FT BT8TRP_TC BD8STRP_FT BD8STRP_FT BD8STRP_FT BD8STRP_FT BD4STRP_FT Description Address Bus [24:20], [15], [9:8], [3:0] Address Bus [19], [11] Address Bus [18:16], [14:12], [7:4] Address Bus [10] Data Bus [15:0] Memory and I/O Read signal Memory and I/O Write signal Data Ready I/O Chip Select I/O Chip Select I/O Chip Select Upper Byte Enable (PD[15:8]) Lower Byte Enable (PD[7:0]) Flash Bank 0 Chip Select Flash Bank 1 Chip Select Upper half Bank 0 Flash Chip Select Lower half Bank 0 Flash Chip Select Upper half Bank 1 Flash Chip Select Lower half Bank 1 Flash Chip Select Muxed Interrupt Lines Qty 12 2 10 1 16 1 1 1 4 1 3 1 1 1 1 1 1 1 1 4 I/O I/O O O O O I I O O O BD4STRP_FT BD8STRUP_FT BD8STRUP_FT BD8STRUP_FT BD8STRUP_FT BD8STRUP_FT BD4STRP_FT BD4STRP_FT BD8STRP_FT BD8STRUP_FT BD8STRP_FT Data Bus Data Bus Address Bus Primary Chip Selects Secondary Chip Selects Data I/O Ready Primary / Secondary Interrupt Request Primary / Secondary DMA Request Primary / Secondary DMA Acknowledge Primary / Secondary IO Read Primary / Secondary IO Write 4 12 3 2 2 1 2 2 2 2 2 VGA CONTROLLER RED, GREEN, BLUE O VDDCO VSYNC, HSYNC I/O BD4STRP_FT VREF_DAC I ANA RSET I ANA COMP I ANA COL_SEL O BD4STRP_FT I2C INTERFACE SCL / DDC[1] SDA / DDC[0] Red, Green, Blue Vertical & Horizontal Synchronisations DAC Voltage reference Resistor Set Compensation Colour Select 3 2 1 1 1 1 I/O BD4STRUP_FT I/O BD4STRUP_FT IC Interface - Clock / VGA DDC[1] IC Interface - Data / VGA DDC[0] 1 1 TFT INTERFACE TFTR[5:2] O BD4STRP_TC TFTR[1:0] O BD4STRP_FT TFTG[5:2] O BD4STRP_TC ,TFTG[1:0] O BD4STRP_FT Note1; See Table 2-3 for buffer type descriptions Red Red Green Green 4 2 4 2 16/111 Issue 1.0 - July 24, 2002 PIN DESCRIPTION Table 2-2. Definition of Signal Pins Signal Name TFTB[5:2] TFTB[1:0] TFTLINE TFTFRAME TFTDE TFTENVDD, TFTENVCC TFTPWM TFTDCLK Dir O O O O O Buffer Type1 BD4STRP_TC BD4STRP_FT BD8STRP_TC BD4STRP_TC BD4STRP_TC Description Blue Blue Horizontal Sync Vertical Sync Data Enable Enable Vdd & Vcc of flat panel PWM back-light control Dot clock for Flat Panel Qty 4 2 1 1 1 2 1 1 O BD4STRP_TC O BD8STRP_TC O BT8TRP_TC VIDEO INPUT PORT VCLK I/O BD8STRP_FT VIN[7:0] I BD4STRP_FT ODD_EVEN# I/O BD4STRP_FT VCS I/O BD4STRP_FT USB INTERFACE OC USBDPLS[0]1 USBDMNS[0]1 USBDPLS[1]1 USBDMNS[1]1 POWERON1 27-33 MHz Video Input Port Clock Video Input Data Bus Video Input Odd/even Field Video Input Horizontal Sync 1 8 1 1 I TLCHTU_TC Over Current Detect Universal Serial Bus Port 0 Universal Serial Bus Port 1 USB power supply lines 1 2 2 1 I/O USBDS_2V5 I/O USBDS_2V5 O BT4CRP SERIAL CONTROLLER CTS0#, CTS1# I DCD0#, DCD1# I DSR0#, DSR1# I DTR0#, DTR1# O RI0#, RI1# I RTS0#, RTS1# O RXD0, RXD1 I TXD0, TXD1 O TLCHT_FT TLCHT_FT TLCHT_FT BD4STRP_TC TLCHT_FT BD4STRP_TC TLCHT_FT BD4STRP_TC Clear to send, MSR[4] status bit Data Carrier detect, MSR[7] status bit Data set ready, MSR[5] status bit. Data terminal ready, MSR[0] status bit Ring indicator, MSR[6] status bit Request to send, MSR[1] status bit Receive data, Input Serial Input Transmit data, Serial Output 2 2 2 2 2 2 2 2 KEYBOARD & MOUSE INTERFACE KBCLK I/O BD4STRP_TC KBDATA I/O BD4STRP_TC MCLK I/O BD4STRP_TC MDATA I/O BD4STRP_TC PARALLEL PORT PE SLCT BUSY# ERR# ACK# PDIR# STROBE# INIT# AUTOFD# SLCTIN# PPD[7:0] Keyboard Clock Line Keyboard Data Line Mouse Clock Line Mouse Data Line 1 1 1 1 I I I I I O O O O O I/O BD14STARP_FT BD14STARP_FT BD14STARP_FT BD14STARP_FT BD14STARP_FT BD14STARP_FT BD14STARP_FT BD14STARP_FT BD14STARP_FT BD14STARP_FT BD14STARP_FT Paper End SELECT BUSY ERROR Acknowledge Parallel Device Direction PCS / STROBE# INIT Automatic Line Feed SELECT IN Data Bus 1 1 1 1 1 1 1 1 1 1 8 Note1; See Table 2-3 for buffer type descriptions Issue 1.0 - July 24, 2002 17/111 PIN DESCRIPTION Table 2-2. Definition of Signal Pins Signal Name GPIO SIGNALS GPIO[15:0] JTAG TCLK TRST TDI TMS TDO Dir Buffer Type1 Description Qty I/O BD4STRP_FT General Purpose IOs 16 I I I I O TLCHT_FT TLCHT_FT TLCHTD_FT TLCHT_FT BT8TRP_TC Test Clock Test Reset Test Data Input Test Mode Set Test Data output 1 1 1 1 MISCELLANEOUS SCAN_ENABLE I TLCHTD_FT Test Pin - Reserved SPKRD O BD4STRP_FT Speaker Device Output Note1; See Table 2-3 for buffer type descriptions 1 1 Table 2-3. Buffer Type Descriptions Buffer ANA OSCI13B BT4CRP BT8TRP_TC BD4STRP_FT BD4STRUP_FT BD4STRP_TC BD8STRP_FT BD8STRUP_FT BD8STRP_TC BD8TRP_TC BD8PCIARP_FT BD14STARP_FT BD16STARUQP_TC SCHMITT_FT TLCHT_FT TLCHT_TC TLCHTD_TC TLCHTU_TC USBDS_2V5 VDDCO Description Analog pad buffer Oscillator, 13 MHz, HCMOS LVTTL Output, 4 mA drive capability, Tri-State Control LVTTL Output, 8 mA drive capability, Tri-State Control, Schmitt trigger LVTTL Bi-Directional, LVTTL Bi-Directional, LVTTL Bi-Directional, LVTTL Bi-Directional, LVTTL Bi-Directional, LVTTL Bi-Directional, LVTTL Bi-Directional, LVTTL Bi-Directional, LVTTL Bi-Directional, LVTTL Bi-Directional, 4 mA drive capability, Schmitt trigger, 5V tolerant 4 mA drive capability, Schmitt trigger, Pull-Up, 5V tolerant 4 mA drive capability, Schmitt trigger 8 mA drive capability, Schmitt trigger, 5V tolerant 8 mA drive capability, Schmitt trigger, Pull-Up, 5V tolerant 8 mA drive capability, Schmitt trigger 8 mA drive capability, Schmitt trigger 8 mA drive capability, PCI compatible, 5V tolerant 14 mA drive capability, Schmitt trigger, IEEE1284 compliant, 5V tolerant 16 mA drive capability, Schmitt trigger LVTTL Input, Schmitt trigger, 5V tolerant LVTTL Input, 5V tolerant LVTTL Input LVTTL Input, Pull-Down LVTTL Input, Pull-Up USB 1.1 compliant pad buffer Analog output pad 18/111 Issue 1.0 - July 24, 2002 PIN DESCRIPTION 2.2. SIGNAL DESCRIPTIONS DEV_CLK 24 MHz Peripheral Clock (floppy drive). This 24 MHz signal is provided as a convenience for the system integration of a Floppy Disk driver function in an external chip. This clock signal is not available in Local Bus mode. DCLK 135 MHz Dot Clock. This is the dot clock, which drives graphics display cycles. Its frequency can be as high as 135 MHz, and it is required to have a worst case duty cycle of 60-40. For further details, refer to Section 3.1.4. bit 4. 2.2.1. BASIC CLOCKS AND RESETS SYSRSTI# System Reset/Power good. This input is low when the reset switch is depressed. Otherwise, it reflects the power supply's power good signal. PWGD is asynchronous to all clocks, and acts as a negative active reset. The reset circuit initiates a hard reset on the rising edge of PWGD. Note that while Reset is being asserted, the signals on the device pins are in an unknown state. SYSRSTO# Reset Output to System. This is the system reset signal and is used to reset the rest of the components (not on Host bus) in the system. The ISA bus reset is an externally inverted buffered version of this output and the PCI bus reset is an externally buffered version of this output. XTALI 14.3 MHz Crystal Input XTALO 14.3 MHz Crystal Output. These pins are provided for the connection of an external 14.318 MHz crystal to provide the reference clock for the internal frequency synthesizer, from which the HCLK and CLK24M signals are generated. PCI_CLKI 33 MHz PCI Input Clock. This signal must be connected to a clock generator and is usually connected to PCI_CLKO. PCI_CLKO 33 MHz PCI Output Clock. This is the master PCI bus clock output. ISA_CLK ISA Clock Output (also Multiplexer Select Line For IPC). This pin produces the Clock signal for the ISA bus. It is also used with ISA_CLK2X as the multiplexer control lines for the Interrupt Controller Interrupt input lines. This is a divided down version of the PCICLK or OSC14M. ISA_CLKX2 ISA Clock Output (also Multiplexer Select Line For IPC). This pin produces a signal at twice the frequency of the ISA bus Clock signal. It is also used with ISA_CLK as the multiplexer control lines for the Interrupt Controller Interrupt input lines. CLK14M ISA bus synchronisation clock. This is the buffered 14.318 MHz clock to the ISA bus. HCLK Host Clock. This is the host clock. Its frequency can vary from 25 to 66 MHz. All host transactions and PCI transactions are synchronized to this clock. Host transactions executed by the DRAM controller are also driven by this clock. 2.2.2. MEMORY INTERFACE MCLKI Memory Clock Input. This clock is driving the SDRAM controller, the graphics engine and display controller. This input should be a buffered version of the MCLKO signal with the track lengths between the buffer and the pin matched with the track lengths between the buffer and the Memory Banks. MCLKO Memory Clock Output. This clock drives the Memory Banks on board and is generated from an internal PLL. The STPC Atlas MClock signal can run up to 100MHz reliably, but PCB layout is so critical that the maximum guaranteed speed is 90MHz CS#[1:0] Chip Select These signals are used to disable or enable device operation by masking or enabling all SDRAM inputs except MCLK, CKE, and DQM. CS#[2]/MA[11] Chip Select/Bank Address This pin is CS#[2] in the case when 16-Mbit devices are used. For all other densities, it becomes MA[11]. CS#[3]/MA[12]/BA[1] Chip Select/ Memory Address/ Bank Address This pin is CS#[3] in the case when 16 Mbit devices are used. For all other densities, it becomes MA[12] when 2 internal banks devices are used and BA[1] when 4 internal bank devices are used. MA[10:0] Memory Address. Multiplexed row and column address lines. BA[0] Bank Address. Internal bank address line. MD[63:0] Memory Data. This is the 64-bit memory data bus. This bus is also used as input at the rising edge of SYSRSTI# to latch in power-up configuration information into the ADPC strap registers. RAS#[1:0] Row Address Strobe. There are two active-low row address strobe output signals. The RAS# signals drive the memory devices directly without any external buffering. Issue 1.0 - July 24, 2002 19/111 PIN DESCRIPTION CAS#[1:0] Column Address Strobe. There are two active-low column address strobe output signals. The CAS# signals drive the memory devices directly without any external buffering. MWE# Write Enable. Write enable specifies whether the memory access is a read (MWE# = H) or a write (MWE# = L). This single write enable controls all DRAMs. The MWE# signals drive the memory devices directly without any external buffering. DEVSEL# prior to the subtractive decode phase of the current PCI transaction. PAR Parity Signal Transactions. This is the parity signal of the PCI bus. This signal is used to guarantee even parity across AD[31:0], CBE[3:0]#, and PAR. This signal is driven by the master during the address phase and data phase of write transactions. It is driven by the target during data phase of read transactions. (Its assertion is identical to that of the AD bus delayed by one PCI clock cycle) PERR# Parity Error AD[31:0] PCI Address/Data. This is the 32-bit multiplexed address and data bus of the PCI. This bus is driven by the master during the address phase and data phase of write transactions. It is driven by the target during data phase of read transactions. PBE[3:0]# Bus Commands/Byte Enables. These are the multiplexed command and Byte enable signals of the PCI bus. During the address phase they define the command and during the data phase they carry the Byte enable information. These pins are inputs when a PCI master other than the STPC Atlas owns the bus and outputs when the STPC Atlas owns the bus. FRAME# Cycle Frame. This is the frame signal of the PCI bus. It is an input when a PCI master owns the bus and is an output when STPC Atlas owns the PCI bus. TRDY# Target Ready. This is the target ready signal of the PCI bus. It is driven as an output when the STPC Atlas is the target of the current bus transaction. It is used as an input when STPC Atlas initiates a cycle on the PCI bus. IRDY# Initiator Ready. This is the initiator ready signal of the PCI bus. It is used as an output when the STPC Atlas initiates a bus cycle on the PCI bus. It is used as an input during the PCI cycles targeted to the STPC Atlas to determine when the current PCI master is ready to complete the current transaction. STOP# Stop Transaction. STOP# is used to implement the disconnect, retry and abort protocol of the PCI bus. It is used as an input for the bus cycles initiated by the STPC Atlas and is used as an output when a PCI master cycle is targeted to the STPC Atlas. DEVSEL# Device Select. This signal is used as an input when the STPC Atlas initiates a bus cycle on the PCI bus to determine if a PCI slave device has decoded itself to be the target of the current transaction. It is asserted as an output either when the STPC Atlas is the target of the current PCI transaction or when no other device asserts SERR# System Error. This is the system error signal of the PCI bus. It may, if enabled, be asserted for one PCI clock cycle if target aborts a STPC Atlas initiated PCI transaction. Its assertion by either the STPC Atlas or by another PCI bus agent will trigger the assertion of NMI to the host CPU. This is an open drain output. LOCK# PCI Lock. This is the lock signal of the PCI bus and is used to implement the exclusive bus operations when acting as a PCI target agent. PCI_REQ#[2:0] PCI Request. These pins are the three external PCI master request pins. They indicates to the PCI arbiter that the external agents desire use of the bus. PCI_GNT#[2:0] PCI Grant. These pins indicate that the PCI bus has been granted to the master requesting it on its PCI_REQ#. PCI_INT#[3:0] PCI Interrupt Request. These are the PCI bus interrupt signals. They are to be encoded before connection to the STPC Atlas using ISACLK and ISACLKX2 as the input selection strobes. 2.2.3. PCI INTERFACE 2.2.4. ISA BUS INTERFACE LA[23:17] Unlatched Address. These unlatched ISA Bus pins address bits 23-17 on 16-bit devices. When the ISA bus is accessed by any cycle initiated from the PCI bus, these pins are in output mode. When an ISA bus master owns the bus, these pins are tristated. SA[19:0] Unlatched Address. These are the 20 low bits of the system address bus of ISA. These pins are used as an input when an ISA bus master owns the bus and are outputs at all other times. SD[15:0] I/O Data Bus (ISA). These are the external ISA databus pins. IOCHRDY IO Channel Ready. IOCHRDY is the IO channel ready signal of the ISA bus and is driven as an output in response to an ISA master cycle targeted to the host bus or an internal register of 20/111 Issue 1.0 - July 24, 2002 PIN DESCRIPTION the STPC Atlas. The STPC Atlas monitors this signal as an input when performing an ISA cycle on behalf of the host CPU, DMA master or refresh. ISA masters which do not monitor IOCHRDY are not guaranteed to work with the STPC Atlas since the access to the system memory can be considerably delayed due to CRT refresh or a write back cycle. ALE Address Latch Enable. This is the address latch enable output of the ISA bus and is asserted by the STPC Atlas to indicate that LA23-17, SA190, AEN and SBHE# signals are valid. The ALE is driven high during refresh, DMA master or an ISA master cycles by the STPC Atlas. ALE is driven low after reset. BHE# System Bus High Enable. This signal, when asserted, indicates that a data Byte is being transferred on SD15-8 lines. It is used as an input when an ISA master owns the bus and is an output at all other times. MEMR# Memory Read. This is the memory read command signal of the ISA bus. It is used as an input when an ISA master owns the bus and is an output at all other times. The MEMR# signal is active during refresh. MEMW# Memory Write. This is the memory write command signal of the ISA bus. It is used as an input when an ISA master owns the bus and is an output at all other times. SMEMR# System Memory Read. The STPC Atlas generates SMEMR# signal of the ISA bus only when the address is below one MByte or the cycle is a refresh cycle. SMEMW# System Memory Write. The STPC Atlas generates SMEMW# signal of the ISA bus only when the address is below one MByte. IOR# I/O Read. This is the IO read command signal of the ISA bus. It is an input when an ISA master owns the bus and is an output at all other times. IOW# I/O Write. This is the IO write command signal of the ISA bus. It is an input when an ISA master owns the bus and is an output at all other times. MASTER# Add On Card Owns Bus. This signal is active when an ISA device has been granted bus ownership. MCS16# Memory Chip Select16. This is the decode of LA23-17 address pins of the ISA address bus without any qualification of the command signal lines. MCS16# is always an input. The STPC Atlas ignores this signal during IO and refresh cycles. IOCS16# IO Chip Select16. This signal is the decode of SA15-0 address pins of the ISA address bus without any qualification of the command signals. The STPC Atlas does not drive IOCS16# (similar to PC-AT design). An ISA master access to an internal register of the STPC Atlas is executed as an extended 8-bit IO cycle. REF# Refresh Cycle. This is the refresh command signal of the ISA bus. It is driven as an output when the STPC Atlas performs a refresh cycle on the ISA bus. It is used as an input when an ISA master owns the bus and is used to trigger a refresh cycle. The STPC Atlas performs a pseudo hidden refresh. It requests the host bus for two host clocks to drive the refresh address and capture it in external buffers. The host bus is then relinquished while the refresh cycle continues on the ISA bus. AEN Address Enable. Address Enable is enabled when the DMA controller is the bus owner to indicate that a DMA transfer will occur. The enabling of the signal indicates to IO devices to ignore the IOR#/IOW# signal during DMA transfers. IOCHCK# IO Channel Check. IO Channel Check is enabled by any ISA device to signal an error condition that can not be corrected. NMI signal becomes active upon seeing IOCHCK# active if the corresponding bit in Port B is enabled. GPIOCS# I/O General Purpose Chip Select 1. This output signal is used by the external latch on ISA bus to latch the data on the SD[7:0] bus. The latch can be use by PMU unit to control the external peripheral devices to power down or any other desired function. RTCRW# Real Time Clock RW#. This pin is used as RTCRW#. This signal is asserted for any I/O write to port 71h. RTCDS# Real Time Clock DS. This pin is used as RTCDS#. This signal is asserted for any I/O read to port 71h. Its polarity complies with the DS pin of the MT48T86 RTC device when configured with Intel timings. RTCAS Real time clock address strobe. This signal is asserted for any I/O write to port 70h. RMRTCCS# ROM/Real Time clock chip select. This pin is a multi-function pin. This signal is asserted if a ROM access is decoded during a memory cycle. It should be combined with MEMR# or MEMW# signals to properly access the ROM. During an IO cycle, this signal is asserted if access to the Real Time Clock (RTC) is decoded. It should be combined with IOR# or IOW# signals to properly access the real time clock. Issue 1.0 - July 24, 2002 21/111 PIN DESCRIPTION IRQ_MUX[3:0] Multiplexed Interrupt Request. These are the ISA bus interrupt signals. They are to be encoded before connection to the STPC Atlas using ISACLK and ISACLKX2 as the input selection strobes. Note that IRQ8B, which by convention is connected to the RTC, is inverted before being sent to the interrupt controller, so that it may be connected directly to the IRQ# pin of the RTC. ISAOE# Bidirectional OE Control. This signal controls the OE signal of the external transceiver that connects the IDE DD bus and ISA SA bus. KBCS# Keyboard Chip Select. This signal is asserted if a keyboard access is decoded during a I/O cycle. ZWS# Zero Wait State. This signal, when asserted by addressed device, indicates that current cycle can be shortened. DACK_ENC[2:0] DMA Acknowledge. These are the ISA bus DMA acknowledge signals. They are encoded by the STPC Atlas before output and should be decoded externally using ISACLK and ISACLKX2 as the control strobes. DREQ_MUX[1:0] ISA Bus Multiplexed DMA Request. These are the ISA bus DMA request signals. They are to be encoded before connection to the STPC Atlas using ISACLK and ISACLKX2 as the input selection strobes. TC ISA Terminal Count. This is the terminal count output of the DMA controller and is connected to the TC line of the ISA bus. It is asserted during the last DMA transfer, when the Byte count expires. Cards (asserted when the switch is set to write protect). BVD1, BVD2 Battery Voltage Detect. These inputs will be generated by memory PC Cards that include batteries and are an indication of the condition of the batteries. BVD1 and BVD2 are kept asserted high when the battery is in good condition. Ready/busy/Interrupt READY#/BUSY#/IREQ# request. This input is driven low by memory PC Cards to signal that their circuits are busy processing a previous write command. WAIT# Bus Cycle Wait. This input is driven by the PC Card to delay completion of the memory or I/O cycle in progress. OE# Output Enable. OE# is an active low output which is driven to the PC Card to gate Memory Read data from memory PC Cards. WE#/PRGM# Write Enable. This output is used by the host for gating Memory Write data. WE# is also used for memory PC Cards that have programmable memory. REG# Attribute Memory Select. This output is inactive (high) for all normal accesses to the Main Memory of the PC Card. I/O PC Cards will only respond to IORD# or IOWR# when REG# is active (low). Also see Section 2.2.7. CD1#, CD2# Card Detect. These inputs provide for the detection of correct card insertion. CD#1 and CD#2 are positioned at opposite ends of the connector to assist in the detection process. These inputs are internally grounded on the PC Card therefore they will be forced low whenever a card is inserted in a socket. CE1#, CE2# Card Enable. These are active low output signals provided from the PCIC. CE#1 enables even Bytes, CE#2 odd Bytes. ENABLE# Enable. This output is used to activate/ select a PC Card socket. ENABLE# controls the external address buffer logic.C card has been detected (CD#1 and CD#2 = '0'). ENIF# ENIF. This output is used to activate/select a PC Card socket. EXT_DIR EXternal Transceiver Direction Control. This output is high during a read and low during a write. The default power up condition is write (low). Used for both Low and High Bytes of the Data Bus. VCC_EN#, VPP1_EN0, VPP1_EN1, VPP 2_EN0, VPP2_EN1 Power Control. Five output signals 2.2.5. PCMCIA INTERFACE RESET Card Reset. This output forces a hard reset to a PC Card. A[25:0] Address Bus. These are the 25 low bits of the system address bus of the PCMCIA bus. These pins are used as an input when an PCMCIA bus owns the bus and are outputs at all other times. D[15:0] I/O Data Bus (PCMCIA). These are the external PCMCIA databus pins. IORD# I/O Read. This output is used with REG# to gate I/O read data from the PC Card, (only when REG# is asserted). IOWR# I/O Write. This output is used with REG# to gate I/O write data from the PC Card, (only when REG# is asserted). WP Write Protect. This input indicates the status of the Write Protect switch (if fitted) on memory PC 22/111 Issue 1.0 - July 24, 2002 PIN DESCRIPTION used to control voltages (VPP1, VPP2 and VCC) to a PC Card socket. Also see Section 13.7.5. GPI# General Purpose Input. This signal is hardwired to 1. 2.2.8. IDE INTERFACE DA[2:0] Address. These signals are connected to DA[2:0] of IDE devices directly or through a buffer. If the toggling of signals are to be masked during ISA bus cycles, they can be externally ORed with ISAOE# before being connected to the IDE devices. DD[15:0] Databus. When the IDE bus is active, they serve as IDE signals DD[11:0]. IDE devices are connected to SA[19:8] directly and ISA bus is connected to these pins through two LS245 transceivers. PCS1, PCS3, SCS1, SCS3 Primary & Secondary Chip Selects. These signals are used as the active high primary and secondary master & slave IDE chip select signals. These signals must be externally NANDed with the ISAOE# signal before driving the IDE devices to guarantee it is active only when ISA bus is idle. In Local Bus mode, they just need to be inverted. DIORDY Busy/Ready. This pin serves as IDE signal DIORDY. PIRQ Primary Interrupt Request. SIRQ Secondary Interrupt Request. Interrupt request from IDE channels. PDRQ Primary DMA Request. SDRQ Secondary DMA Request. DMA request from IDE channels. PDACK# Primary DMA Acknowledge. SDACK# Secondary DMA Acknowledge. DMA acknowledge to IDE channels. PDIOR#, PDIOW# Primary I/O Read & Write. SDIOR#, SDIOW# Secondary I/O Read & Write. Primary & Secondary channel read & write. 2.2.6. LOCAL BUS PA[24:0] Address Bus Output. PD[15:0] Data Bus. This is the 16-bit data bus. D[7:0] is the LSB and PD[15:8] is the MSB. PRD#[1:0] Read Control output. These are memory and I/O Read signals. PRD0# is used to read the LSB and PRD1# to read the MSB. PWR#[1:0] Write Control output. These are memory and I/O Write signals. PWR0# is used to write the LSB and PWR1# to write the MSB. PRDY Data Ready input. This signal is used to create wait states on the bus. When high, it completes the current cycle. FCS#[1:0] Two Flash Memory Chip Select outputs. These are the Programmable Chip Select signals for Flash memory. IOCS#[7:0] I/O Chip Select output. These are the Programmable Chip Select signals for up to 4 external I/O devices. PBE#[1:0] Byte Enable. These are the Byte enables that identifies on which databus the date is valid. PBE#[0] corresponds to PD[7:0] and PBE#[1] corresponds to PD[15:8]. These are normally used when 8 bit transfers are transfered across the 16 bit bus. IRQ_MUX#[3:0] Multiplexed Interrupt Lines. 2.2.7. IPC 2.2.9. MONITOR INTERFACE DACK_ENC[2:0] DMA Acknowledge. These are the ISA bus DMA acknowledge signals. They are encoded by the STPC Industrial before output and should be decoded externally using ISACLK and ISACLKX2 as the control strobes. DREQ_MUX[1:0] ISA Bus Multiplexed DMA Request. These are the ISA bus DMA request signals. They are to be encoded before connection to the STPC Industrial using ISACLK and ISACLKX2 as the input selection strobes. TC ISA Terminal Count. This is the terminal count output of the DMA controller and is connected to the TC line of the ISA bus. It is asserted during the last DMA transfer, when the Byte count expires. RED, GREEN, BLUE RGB Video Outputs. These are the 3 analog colour outputs from the RAMDACs. These signals are sensitive to interference, therefore they need to be properly shielded. VSYNC Vertical Synchronisation Pulse. This is the vertical synchronization signal from the VGA controller. HSYNC Horizontal Synchronisation Pulse. This is the horizontal synchronization signal from the VGA controller. VREF_DAC DAC Voltage reference. This pin is an input driving the digital to analog converters. This allows an external voltage reference source to be used. Issue 1.0 - July 24, 2002 23/111 PIN DESCRIPTION RSET Resistor Current Set. This is the reference current input to the RAMDAC. Used to set the fullscale output of the RAMDAC. COMP Compensation. This is the RAMDAC compensation pin. Normally, an external capacitor (typically 10nF) is connected between this pin and VDD to damp oscillations. DDC[1:0] Direct Data Channel Serial Link. These bidirectional pins are connected to CRTC register 3Fh to implement DDC capabilities. They conform to I2C electrical specifications, they have opencollector output drivers which are internally connected to VDD through pull-up resistors. They can instead be used for accessing IC devices on board. DDC1 and DDC0 correspond to SCL and SDA respectively. TFTR5-0, Red Output. TFTG5-0, Green Output. TFTB5-0, Blue Output. TFTENVDD, Enable VDD of Flat Panel. TFTENVCC, Enable VCC of Flat Panel. PWM PWM Back-Light Control. This PWM is clocked by the PCI clock. TFTDCLK, Dot clock for the Flat Panel. 2.2.12. USB INTERFACE OC OVER CURRENT DETECT This signal is used to monitor the status of the USB power supply lines of both devices. USB port are disabled when OC signal is asserted. USBDPL0, USBDMNS0 UNIVERSAL SERIAL BUS DATA 0 This signal pair comprises the differential data signal for USB port 0. USBDPL1, USBDMNS1 UNIVERSAL SERIAL BUS PORT 1 This signal pair comprises the differential data signal for USB port 1. POWERON USB power supply lines 2.2.10. VIDEO INTERFACE VCLK Pixel Clock Input.This signal is used to synchronise data being transferred from an external video device to either the frame buffer, or alternatively out the TV output in bypass mode. This pin can be sourced from STPC if no external VCLK is detected, or can be input from an external video clock source. VIN[7:0] YUV Video Data Input ITU-R 601 or 656. Time multiplexed 4:2:2 luminance and chrominance data as defined in ITU-R Rec601-2 and Rec656 (except for TTL input levels). This bus typically carries a stream of Cb,Y,Cr,Y digital video at VCLK frequency, clocked on the rising edge (by default) of VCLK. VCS Line synchronisation Input. This is the horizontal synchronisation of the incomming CCIR601 video. The signal is synchronous to rising edge of VCLK. ODD_EVEN Frame Synchronisation Output. This is the vertical synchronisation of the incomming CCIR601 video. The signal is synchronous to rising edge of VCLK. The default polarity for this pin is: - odd (not-top) field: LOW level - even (bottom) field: HIGH level 2.2.13. SERIAL INTERFACE RXD0, RXD1 Serial Input. Data is clocked in using RCLK/16. TXD0, TXD1 Serial Output. Data is clocked out using TCLK/16 (TCLK=BAUD#). DCD0#, DCD1# Input Data carrier detect. RI0#, RI1# Input Ring indicator. DSR0#, DSR1# Input Data set ready. CTS0#, CTS1# Input Clear to send. RTS0#, RTS1# Output Request to send. DTR0#, DTR1# Output Data terminal read. 2.2.11. TFT INTERFACE SIGNALS 2.2.14. KEYBOARD/MOUSE INTERFACE The TFT (Thin Film Transistor) interface converts signals from the CRT controller into control signals for an external TFT Flat Panel. The signals are listed below. TFTFRAME, Vertical Sync. pulse Output. TFTLINE, Horizontal Sync. Pulse Output. TFTDE, Data Enable. 24/111 KBCLK, Keyboard Clock line. Keyboard data is latched by the controller on each negative clock edge produced on this pin. The keyboard can be disabled by pulling this pin low by software control. KBDATA, Keyboard Data Line. 11-bits of data are shifted serially through this line when data is being transferred. Data is synchronised to KBCLK. Issue 1.0 - July 24, 2002 PIN DESCRIPTION MCLK, Mouse Clock line. Mouse data is latched by the controller on each negative clock edge produced on this pin. The mouse can be disabled by pulling this pin low by software control. MDATA, Mouse Data Line. 11-bits of data are shifted serially through this line when data is being transferred. Data is synchronised to MCLK. SLCTIN# Select In. Printer select output. PPD[7-0] Parallel Port Data Lines Data transfer lines to printer. Bidirectional depending on modes. 2.2.16. MISCELLANEOUS SPKRD Speaker Drive. This is the output to the speaker and is the AND of the counter 2 output with bit 1 of Port 61h and drives an external speaker driver. This output should be connected to a 7407 type high voltage driver. SCAN_ENABLE Reserved. This pin is reserved for Test and Miscellaneous functions. It has to be set to `0' or connected to ground in normal operation. COL_SEL Colour Select. Can be used for Picture in Picture function. Note however that this signal, brought out from the video pipeline, is not in sync with the VGA output signals, i.e. the VGA signals run four clock cycles after the Col_Sel signal. 2.2.15. PARALLEL PORT PE Paper End. Input status signal from printer. SLCT Printer Select. Printer selected input. BUSY# Printer Busy. Input status signal from printer. ERR# Error. Input status signal from printer. ACK# Acknowledge. Input status signal from printer. PDDIR# Parallel Device Direction. Bidirectional control line output. STROBE# PCS/Strobe#. Data transfer strobe line to printer. INIT# Initialize Printer. This output sends an initialize command to the connected printer. AUTOFD# Automatic Line feed. This output sends a command to the connected printer to automatically generate line feed on received carriage returns. 2.2.17. JTAG INTERFACE TCLK Test clock TDI Test data input TMS Test mode input TDO Test data output TRST Test reset input Issue 1.0 - July 24, 2002 25/111 PIN DESCRIPTION 2.3. SIGNAL DETAIL The resulting interface is then dynamically muxed with the IDE Interface. The muxing between ISA, LOCAL BUS and PCMCIA is performed by external strap options. Table 2-4. Multiplexed Signals (on the same pin) IDE Pin Name DIORDY DA[2] DA[1:0] SCS3,SCS1 PCS3,PCS1 DD[15] DD[14] DD[13:12] DD[11:0] ISA Pin Name IOCHRDY LA[19] LA[18:17] LA[23:22] LA[21:20] RMRTCCS# KBCS# RTCRW#, RTCDS# SA[19:8] SD[15:0] RTCAS DEV_CLK SA[3] SA[2:0] SMEMW# IOCS16# MASTER# MCS16# DACK_ENC [2:0] TC SA[7:4] ZWS# GPIOCS# IOCHCK# REF# IOW# IOR# MEMR# ALE AEN BHE# MEMW# SMEMR# DREQ_MUX#[1:0] Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z ISAOE# = 0 PCMCIA Pin Names =0 A[25:24] A[23:22] A[21:20] ROMCS# Hi-Z Hi-Z A[19:8] D[15:0] =0 DEV_CLK A[3] A[2:0] VPP_PGM WP/IOIS16# BVD1 =0 = 0x04 =0 A[7:4] GPI# VCC5_EN BVD2 RESET IOWR# IORD# =0 =0 WAIT# OE# =0 VCC3_EN CE2#, CE1# Hi-Z VPP_VCC WE# REG# READY# CD1#, CD2# ISAOE# = 0 Local Bus Pin Name ISAOE# = 1 PD[15:0] FCS0# FCS1# PRDY IOCS#[2:0] PBE#[1] PBE#[0] PRD# PWR# PA[2:0] PA[3] PA[7:4] PA[8] PA[9] PA[10] PA[11] PA[12] PA[13] PA[14] PA[15] PA[16] PA[17] PA[18] PA[19] PA[21:20] PA[22] PA[23] PA[24] IOCS#[7] IOCS#[6] IOCS#[5], IOCS#[4] IOCS#[3] 26/111 Issue 1.0 - July 24, 2002 PIN DESCRIPTION Table 2-5. Signal value on Reset Signal Name BASIC CLOCKS AND RESETS XTALO ISA_CLK ISA_CLK2X OSC14M DEV_CLK HCLK PCI_CLKO DCLK MEMORY CONTROLLER MCLKO CS#[3:1] CS#[0] MA[10:0], BA[0] RAS#[1:0], CAS#[1:0] MWE#, DQM[7:0] MD[63:0] PCI INTERFACE AD[31:0] CBE[3:0], PAR FRAME#, TRDY#, IRDY# STOP#, DEVSEL# PERR#, SERR# PCI_GNT#[2:0] ISA BUS INTERFACE ISAOE# RMRTCCS# LA[23:17] SA[19:0] SD[15:0] BHE#, MEMR# MEMW#, SMEMR#, SMEMW#, IOR#, IOW# REF# ALE, AEN DACK_ENC[2:0] TC GPIOCS# RTCDS#, RTCRW#, KBCS# RTCAS PCMCIA INTERFACE RESET A[23:0] D[15:0] IORD#, IOWR#, OE# WE#, REG# CE2#, CE1#, VCC5_EN, VCC3_EN VPP_PGM, VPP_VCC LOCAL BUS INTERFACE PA[24:0] PD[15:0] PRD# PBE#[1:0], FCS0#, FCS_0H# SYSRSTI# active SYSRSTI# inactive SYSRSTO# active release of SYSRSTO# 14MHz Low 7MHz 14MHz 14MHz 24MHz Oscillating at the speed defined by the strap options. HCLK divided by 2 or 3, depending on the strap options. 17MHz 66MHz if asynchonous mode, HCLK speed if synchronized mode. High High 0x00 SDRAM init sequence: High Write Cycles High Input 0x0000 Low Input Input Input High High Hi-Z Unknown 0xFFFXX Unknown Unknown Unknown Unknown Low Input Input Hi-Z Hi-Z Unknown Unknown Unknown Unknown Unknown High High Low Unknown Unknown Unknown High First prefetch cycles when not in Local Bus mode. Low 0x00 0xFFF03 0xFF High High High First prefetch cycles when in ISA or PCMCIA mode. Address start is 0xFFFFF0 0x04 Low High Low High 0x00 0xFF High First prefetch cycles using RMRTCCS# 0xFF High First prefetch cycles Issue 1.0 - July 24, 2002 27/111 PIN DESCRIPTION Table 2-5. Signal value on Reset Signal Name FCS_0L#, FCS1#, FCS_1H#, FCS_1L# PWR#, IOCS#[7:0] IDE CONTROLLER DD[15:0] DA[2:0] PCS1, PCS3, SCS1, SCS3 PDACK#, SDACK# PDIOR#, PDIOW#, SDIOR#, SDIOW# VGA CONTROLLER RED, GREEN, BLUE VSYNC, HSYNC COL_SEL I2C INTERFACE SCL / DDC[1] SDA / DDC[0] TFT INTERFACE TFT[R,G,B][5:0] TFTLINE, TFTFRAME TFTDE, TFTENVDD, TFTENVCC, TFTPWM TFTDCLK USB INTERFACE USBDPLS[1:0]1 USBDMNS[1:0]1 POWERON1 SERIAL CONTROLLER TXD0, RTS0#, DTR0# TXD1, RTS1#, DTR1# KEYBOARD & MOUSE INTERFACE KBCLK, MCLK KBDATA, MDATA PARALLEL PORT PDIR#, INIT# STROBE#, AUTOFD# SLCTIN# PPD[7:0] GPIO SIGNALS GPIO[15:0] JTAG TDO MISCELLANEOUS SPKRD SYSRSTI# active High High 0xFF Unknown Unknown High High Black Low Unknown Input Input 0x00,0x00,0x00 Low Low Oscillating at DCLK speed Low High Unknown High High Low Input Low High Unknown Unknown High High Low SYSRSTI# inactive SYSRSTO# active release of SYSRSTO# Low Low Low Low 0x00 28/111 Issue 1.0 - July 24, 2002 PIN DESCRIPTION Table 2-6. Pinout Table 2-6. Pinout Pin# D15 C15 AF21 AF22 AF23 AF24 E15 A16 AB18 AB24 AB25 AC18 Pin Name SYSRSETI# SYSRSETO# XTALI XTALO PCI_CLKI PCI_CLKO ISA_CLK ISA_CLK2X OSC14M HCLK DEV_CLK1/FCS1# DCLK Pin# Pin Name AB3 MD[18] AC1 MD[19] AC3 MD[20] AD2 MD[21] AF3 MD[22] AE4 MD[23] AF4 MD[24] AD5 MD[25] AF5 MD[26] AC6 MD[27] AF6 MD[28] AC7 MD[29] AE7 MD[30] AB8 MD[31] J3 MD[32] J1 MD[33] K4 MD[34] K2 MD[35] L5 MD[36] L3 MD[37] L1 MD[38] M4 MD[39] M2 MD[40] N5 MD[41] N3 MD[42] N1 MD[43] P2 MD[44] P4 MD[45] R1 MD[46] R3 MD[47] AA5 MD[48] AB2 MD[49] AB4 MD[50] AC2 MD[51] AD1 MD[52] AE3 MD[53] AD4 MD[54] AC5 MD[55] AB6 MD[56] AE5 MD[57] AB7 MD[58] AD6 MD[59] AE6 MD[60] AD7 MD[61] AF7 MD[62] AC8 MD[63] U1 CS#[0] U2 CS#[1] Y3 CS#[2]/MA[11] Y4 CS#[3]/MA[12]/BA[1] T2 DQM[0] Note1; This signal is multiplexed see Table 2-4 Pin# T4 Y5 AA2 T3 T5 AA1 AA3 Table 2-6. Pinout Pin Name DQM[1] DQM[2] DQM[3] DQM[4] DQM[5] DQM[6] DQM[7] AF20 MCLKI AF19 MCLKO U5 MA[0] V1 MA[1] V2 MA[2] V3 MA[3] V4 MA[4] V5 MA[5] W1 MA[6] W2 MA[7] W3 MA[8] W5 MA[9] Y1 MA[10] Y2 BA[0] U3 RAS#[0] U4 RAS#[1] R5 CAS#[0] T1 CAS#[1] R4 MWE# J4 MD[0] J2 MD[1] K5 MD[2] K3 MD[3] K1 MD[4] L4 MD[5] L2 MD[6] M5 MD[7] M3 MD[8] M1 MD[9] N4 MD[10] N2 MD[11] P1 MD[12] P3 MD[13] P5 MD[14] R2 MD[15] AA4 MD[16] AB1 MD[17] Note1; This signal is multiplexed see Table 2-4 B3 AD[0] A3 AD[1] C4 AD[2] B4 AD[3] A4 AD[4] D5 AD[5] C5 AD[6] B5 AD[7] A5 AD[8] D6 AD[9] C6 AD[10] B6 AD[11] A6 AD[12] E7 AD[13] D7 AD[14] C7 AD[15] A9 AD[16] E10 AD[17] C10 AD[18] B10 AD[19] A10 AD[20] E11 AD[21] D11 AD[22] C11 AD[23] A11 AD[24] E12 AD[25] D12 AD[26] C12 AD[27] B12 AD[28] A12 AD[29] E13 AD[30] D13 AD[31] E6 CBE[0] B7 CBE[1] B9 CBE[2] B11 CBE[3] C9 FRAME# E9 TRDY# D9 IRDY# B8 STOP# A8 DEVSEL# A7 PAR D8 PERR# Note1; This signal is multiplexed see Table 2-4 Issue 1.0 - July 24, 2002 29/111 PIN DESCRIPTION Table 2-6. Pinout Pin# E8 C8 C14 B14 A14 A13 B13 C13 Pin Name SERR# LOCK# PCI_REQ#[0] PCI_REQ#[1] PCI_REQ#[2] PCI_GNT#[0] PCI_GNT#[1] PCI_GNT#[2] Pin# F25 F23 D20 K25 F24 A22 G23 E21 H22 E26 E25 E24 C22 G22 E17 A23 U25 U26 U24 U23 D22 D24 E23 C26 F22 A24 C23 B23 D26 D25 B24 B15 A15 E14 D14 B16 B22 K26 R23 R24 T22 T23 R25 R26 T25 T24 R22 T26 Table 2-6. Pinout Pin Name SD[15]1 IOCHRDY1 ALE1 BHE#1 MEMR#1 MEMW#1 SMEMR#1 SMEMW#1 IOR#1 IOW#1 MASTER#1 MCS16#1 IOCS16#1 REF#1 AEN1 IOCHCK#1 RTCRW#1 RTCDS#1 RTCAS1/FCS0# RMRTCCS#1 GPIOCS#1 IRQ_MUX[0] IRQ_MUX[1] IRQ_MUX[2] IRQ_MUX[3] DACK_ENC[0] DACK_ENC[1]1 DACK_ENC[2]1 DREQ_MUX[0]1 DREQ_MUX[1]1 TC1 PCI_INT#[0] PCI_INT#[1] PCI_INT#[2] PCI_INT#[3] ISAOE#1 KBCS#1 ZWS#1 PIRQ SIRQ PDRQ SDRQ PDACK# SDACK# PDIOR# PDIOW# SDIOR# SDIOW# Pin# C19 B19 A17 B17 C16 E16 D17 C18 B18 C17 AD8 AF8 AC9 AB10 AF9 AB9 AD9 AE8 AE9 AC10 AB15 AF16 AE16 AC16 AB16 AF17 AE17 AD17 AB17 AD18 AF18 Table 2-6. Pinout Pin Name PA[23] PA[24] FCS_0H FCS_0L FCS_1H FCS_1L IOCS#[4] IOCS#[5] IOCS#[6] IOCS#[7] RED GREEN BLUE VSYNC HSYNC VREF_DAC RSET COMP VDD_DAC VSS_DAC VCLK VIN[0] VIN[1] VIN[2] VIN[3] VIN[4] VIN[5] VIN[6] VIN[7] ODD_EVEN# VCS C20 LA[17] 1 B21 LA[18] 1 B20 LA[19] 1 E19 LA[20] 1 E18 LA[21] 1 C21 LA[22] 1 D19 LA[23] 1 P22 SA[0]1 P23 SA[1]1 P24 SA[2]1 P25 SA[3]1 P26 SA[4]1 N26 SA[5]1 N25 SA[6]1 N24 SA[7]1 N23 SA[8]1 N22 SA[9]1 M26 SA[10] 1 M25 SA[11] 1 M24 SA[12] 1 M23 SA[13] 1 M22 SA[14] 1 L26 SA[15] 1 L25 SA[16] 1 L24 SA[17] 1 L23 SA[18] 1 L22 SA[19] 1 K24 SD[0]1 J26 SD[1]1 J25 SD[2]1 J24 SD[3]1 K23 SD[4]1 K22 SD[5]1 H26 SD[6]1 H25 SD[7]1 H24 SD[8]1 G26 SD[9]1 G25 SD[10]1 G24 SD[11]1 J22 SD[12]1 J23 SD[13]1 F26 SD[14] 1 1; This signal is multiplexed Note see Table 2-4 D18 PA[22] Note1; This signal is multiplexed see Table 2-4 AE10 TFTR0 AF10 TFTR1 AB11 TFTR2 AD11 TFTR3 AE11 TFTR4 AF11 TFTR5 AB12 TFTG0 AC12 TFTG1 AD12 TFTG2 AE12 TFTG3 AF12 TFTG4 AB13 TFTG5 AC13 TFTB0 AD13 TFTB1 AE13 TFTB2 AF13 TFTB3 AF14 TFTB4 Note1; This signal is multiplexed see Table 2-4 30/111 Issue 1.0 - July 24, 2002 PIN DESCRIPTION Table 2-6. Pinout Pin# AE14 AB14 AC14 AF15 AE15 AD15 AC15 AD14 D21 A20 A18 A21 A19 E20 AC22 AC24 AD21 AE24 AC21 AD25 AD22 AC26 AD23 AA22 AE22 AC25 AB21 AD26 AE23 AB23 AD20 AB19 AC20 AB20 Pin Name TFTB5 TFTLINE TFTFRAME TFTDE TFTENVDD TFTENVCC TFTPWM TFTDCLK OC USBDMNS[0] USBDMNS[1] USBDPLS[0] USBDPLS[1] POWERON CTS0# CTS1# DCD0# DCD1# DSR0# DSR1# DTR0# DTR1# RI0# RI1# RTS0# RTS1# RXD0 RXD1 TXD0 TXD1 KBCLK KBDATA MDATA MCLK Pin# AA26 Y24 Y25 Y26 W22 AC19 AD19 C2 C1 D3 D2 D1 E4 E3 E2 E1 F5 F4 F3 F2 G5 G4 G2 H2 J5 H5 H3 H1 G1 AD10 C25 AD16 Y23 AE20 AB26 AE19 AE18 AE21 Table 2-6. Pinout Pin Name PPD[3] PPD[4] PPD[5] PPD[6] PPD[7] SCL / DDC[1] SDA / DDC[0] GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] GPIO[8] GPIO[9] GPIO[10] GPIO[11] GPIO[12] GPIO[13] GPIO[14] GPIO[15] TCLK TRST TDI TMS TDO SCAN_ENABLE COL_SEL SPKRD VDD_DCLK_PLL VDD_DEVCLK_PLL VDD_HCLKI_PLL VDD_HCLKO_PLL VDD_MCLKI_PLL VDD_MCLKO_PLL VDD_PCICLK_PLL Pin# R6 U21 AA10 AA12 AA14 A2 A25 B1 B26 F7 F11 F20 G6 G21 H6 J21 K21 U6 V6 Y6 Y21 AA7 AA16 AA18 AA20 AE01 AE26 AF02 AF25 Table 2-6. Pinout Pin Name VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD AA23 PE W24 SLCT W23 BUSY W25 ERR# W26 ACK# V22 PDDIR V24 STROBE# V25 INIT# V26 AUTOFD# U22 SLCTIN# Y22 PPD[0] AA24 PPD[1] AA25 PPD[2] Note1; This signal is multiplexed see Table 2-4 F13 VDD_CORE F15 VDD_CORE F17 VDD_CORE K6 VDD_CORE M21 VDD_CORE N6 VDD_CORE P21 VDD_CORE Note1; This signal is multiplexed see Table 2-4 A1 GND A26 GND B2 GND B25 GND C3 GND C24 GND D4 GND D10 GND D16 GND D23 GND E5 GND E22 GND F6 GND F8 GND F9 GND F10 GND F12 GND F14 GND F16 GND F18 GND Note1; This signal is multiplexed see Table 2-4 Issue 1.0 - July 24, 2002 31/111 PIN DESCRIPTION Table 2-6. Pinout Pin# Pin Name F19 GND F21 GND H4 GND H21 GND H23 GND J6 GND L6 GND L11:16 GND L21 GND M6 GND M11:16 GND N11:16 GND N21 GND P6 GND P11:16 GND R11:16 GND R21 GND T6 GND Note1; This signal is multiplexed see Table 2-4 Table 2-6. Pinout Pin# Pin Name T11:16 GND T21 GND V21 GND V23 GND W4 GND W6 GND W21 GND AA6 GND AA8 GND AA9 GND AA11 GND AA13 GND AA15 GND AA17 GND AA19 GND AA21 GND AB5 GND AB22 GND Note1; This signal is multiplexed see Table 2-4 Pin# AC4 AC11 AC17 AC23 AD3 AD24 AE2 AE25 AF1 AF26 Table 2-6. Pinout Pin Name GND GND GND GND GND GND GND GND GND GND Reserved G3 F1 Reserved Note1; This signal is multiplexed see Table 2-4 32/111 Issue 1.0 - July 24, 2002 STRAP OPTION 3. STRAP OPTION This chapter defines the STPC Atlas Strap Options and their locations. Some strap options are left programmable for future versions of Signal Designation silicon. The strap options are sampled at a specific point of the boot process. This is shown in detail in Figure 4-3 Location Actual Set to '0' Set to '1' Settings 2 MD1 Reserved Not accessible Pull Up MD2 Index 5F,bit 6 User defined HCLK Speed See Section 3.1.3. MD3 Index 5F,bit 7 User defined PCI_CLKO Divisor Index 4A,bit 1 Pull-up See Section 3.1.1. MD[4] MCLK Synchro (see Section 3.1.1. ) Index 4A,bit 2 User defined Async Sync MD[5] Index 4A,bit 6 User defined MD[6] PCI_CLKO Programming See Section 3.1.1. Index 4A,bit 7 Pull-down MD[7] Index 4A,bit 3 User defined MD[8] ISA / PCMCIA / Local Bus See Section 3.1.1. Index 4A,bit 3 User defined MD[9] MD10 Reserved2 Index 4B,bit 2 Pull down MD11 Reserved2 Index 4B,bit 3 Pull down MD14 CPU clock Multiplication Index 4B,bit 6 Pull-up See Section 3.1.2. Reserved2 Not accessible Pull up MD15 MD16 Reserved2 Not accessible Pull up MD17 PCI_CLKO Divisor Index 4A,bit 0 User defined See Section 3.1.1. MD18 HCLK Pad Direction Index 4C,bit 2 Pull-up Input Output MD19 MCLK Pad Direction Index 4C,bit 3 Pull-up Hi-Z Output MD20 DCLK Pad Direction Index 4C,bit 4 User defined Input Output MD21 Reserved2 Index 5F,bit 0 Pull up MD23 Reserved2 Index 5F,bit 2 Pull up MD24 Index 5F,bit 3 User defined MD25 HCLK PLL Speed Index 5F,bit 4 User defined See Section 3.1.3. MD26 Index 5F,bit 5 User defined MD27 Reserved2 Not accessible Pull up MD28 Reserved2 Not accessible Pull up MD29 Reserved2 Not accessible Pull up MD30 Reserved2 Not accessible Pull up MD31 Reserved2 Not accessible Pull up MD32 Reserved2 Not accessible Pull down 2 MD33 Reserved Not accessible Pull up MD34 Reserved2 Not accessible Pull down MD35 Reserved2 Not accessible Pull down MD36 Local Bus Boot Device Size Index 4B,bit 0 User defined 8-bit 16-bit MD37 Reserved2 Not accessible Pull down MD38 Reserved2 Not accessible Pull down MD40 CPU clock Multiplication Index 4B,bit 7 User defined See Section 3.1.2. Reserved2 Not accessible Pull down MD41 MD42 Reserved2 Not accessible Pull up MD 43 Reserved2 Not accessible Pull down Note1: Strap options on TC/PA[3] and DACK_ENC[2:0]/PA[2:0] are required for all the STPC Atlas Configurations (ISA, PCMCIA, Local Bus). Note2: Must be implemented. Issue 1.0 - July 24, 2002 33/111 STRAP OPTION Actual Set to '0' Set to '1' Settings MD 45 Not accessible User defined CPUCLK/HCKL Deskew Programming See Section 3.1.5. MD 46 Not accessible User defined 2 MD 47 Reserved Not accessible Pull down MD 48 Reserved2 Not accessible Pull up MD 50 Internal UART2 (see Section 3.1.4. ) Index 4C,bit 0 User defined Disable Enable MD 51 Internal UART1 (see Section 3.1.4. ) Index 4C,bit 1 User defined Disable Enable MD 52 Internal Kbd / Mouse (see Section 3.1.4. ) Index 4C,bit 6 User defined Disable Enable MD 53 Internal Parallel Port (see Section 3.1.4. ) Index 4C,bit 7 User defined Disable Enable TC1 Reserved2 Hardware Pull up DACK_ENC[2]1 Reserved2 Hardware Pull up DACK_ENC[1]1 Reserved2 Hardware Pull up DACK_ENC[0]1 Reserved2 Hardware Pull up 1 Note : Strap options on TC/PA[3] and DACK_ENC[2:0]/PA[2:0] are required for all the STPC Atlas Configurations (ISA, PCMCIA, Local Bus). Note2: Must be implemented. Signal Designation Location 34/111 Issue 1.0 - July 24, 2002 STRAP OPTION 3.1. STRAP OPTION REGISTER DESCRIPTION 3.1.1. STRAP REGISTER 0 This register is read only. STRAP0 7 MD[7] 6 MD[6] 5 MD[9] Access = 0022h/0023h 4 MD[8] 3 RSV 2 MD[5] 1 MD[4] Regoffset =04Ah 0 MD[17] This register defaults to the values sampled on the MD pins after reset Bit Number Sampled Mnemonic Description PCICLK PLL set-up: The value sampled on MD[7:6] controls the PCICLK PLL programming according to the PCICLK frequency. MD7 MD6 0 0 PCICLK frequency between 16 & 32 MHz 0 1 PCICLK frequency between 32 & 64 MHz 1 X Reserved Mode selection: MD9 MD8 0 0 ISA mode: ISA enabled, PCMCIA & Local Bus disabled 0 1 PCMCIA mode: PCMCIA enabled, ISA & Local Bus disabled 1 0 Local Bus mode: Local Bus enabled, ISA & PCMCIA disabled 1 1 Reserved Reserved Host Memory synchronization. This bit reflects the value sampled on [MD5] and controls the MCLK/HCLK synchronization. 0: MCLK and HCLK not synchronized 1: MCLK and HCLK synchronized. PCICLK division: These bits reflect the values sampled on [MD4] and MD[17] to select the PCICLK frequency. MD4 MD17 0 X PCI Clock output = HCLK / 4 1 0 PCI Clock output = HCLK / 3 1 1 PCI Clock output = HCLK / 2 Bits 7-6 MD[7:6] Bits 5-4 MD[9:8] Bit 3 Bit 2 Rsv MD[5] Bits 1-0 MD[4], MD[17] Issue 1.0 - July 24, 2002 35/111 STRAP OPTION 3.1.2. STRAP REGISTER 1 This register is read only. STRAP1 7 MD[40] 6 MD[14] 5 RSV Access = 0022h/0023h 4 RSV 3 RSV 2 RSV 1 RSV Regoffset =04Bh 0 MD[36] This register defaults to the values sampled on the MD pins after reset Bit Number Sampled Mnemonic Description CPU Clock Multiplication (486 mode): MD14 MD40 1 0 X1 1 1 X2 All other settings are reserved HCLK maximum speed is 66MHz and in CPU mode X2. Operation in X1 mode is only guaranteed up to 66MHz. Reserved These bits reflect the values sampled on MD[36] and determines the Local Bus Boot device width: 0: 8-bit Boot Device 1: 16-bit Boot Device Bits 7-6 MD[40] & MD[14] Bits 5-1 Bit 0 Rsv MD[36] 36/111 Issue 1.0 - July 24, 2002 STRAP OPTION 3.1.3. HCLK PLL STRAP REGISTER This register is read only. HCLK_STRAP0 7 RSV 6 5 MD[26] Access = 0022h/0023h 4 MD[25] 3 MD[24] 2 1 RSV Regoffset =05Fh 0 This register defaults to the values sampled on the MD pins after reset Bit Number Sampled Bits 7-6 Bits 5-3 Bits 2-0 Mnemonic Rsv MD[26:24] Rsv Description These bits are fixed to `0' These pins reflect the values sampled on MD[26:24] pins respectively and control the Host clock frequency synthesizer as shown in Table 3-1 Reserved Table 3-1. HCLK Frequency Configuration MD[3] 0 0 0 0 MD[2] 0 0 0 0 MD[26] MD[25] 0 0 0 0 0 1 0 1 All other settings are reserved MD[24] 0 1 0 1 HCLK Speed 25 MHz 50 MHz 60 MHz 66 MHz Issue 1.0 - July 24, 2002 37/111 STRAP OPTION 3.1.4. STRAP REGISTER 2 This register is read only with the exception of bit 4 STRAP2 7 MD[53] 6 MD[52] 5 RSV Access = 0022h/0023h 4 MD[20] 3 MD[19] 2 MD[18] 1 MD[51] Regoffset =04Ch 0 MD[50] This register defaults to the values sampled on the MD pins after reset Bit Number Sampled Mnemonic Description This bit reflects the value sampled on MD[53] pin and determines whether the internal Parallel Port Controller is used 0: Internal Parallel Port Controller is disabled 1: Internal Parallel Port Controller is enabled This bit reflects the value sampled on MD[52] pin and determines whether the internal Keyboard controller is used 0: Internal Keyboard Controller is disabled 1: Internal Keyboard Controller is enabled Reserved This bit reflects the value sampled on MD[20] pin and controls the Dot clock pin (DCLK) direction as follows: 0: Input. 1: Output of the internal frequency synthesizer DCLK PLL. This bit reflects the value sampled on MD[19] pin and controls the Memory clock output pin (MCLKO) as follows: 0: Tristated. 1: Output of the internal frequency synthesizer MCLKO PLL. This bit reflects the value sampled on MD[18] pin and controls the Host clock pin (HCLK) direction as follows: 0: Input. 1: Output of the internal frequency synthesizer HCLK PLL. This bit reflects the value sampled on MD[51] pin and determines whether the internal UART1 is enabled: 0: Internal UART1 is disabled 1: Internal UART1 is enabled This bit reflects the value sampled on MD[50] pin and determines whether the internal UART2 is enabled: 0: Internal UART2 is disabled 1: Internal UART2 is enabled Bit 7 MD[53] Bit 6 Bit 5 Bit 4 MD[52] Rsv MD[20] Bit 3 MD[19] Bit 2 MD[18] Bit 1 MD[51] Bit 0 MD[50] 38/111 Issue 1.0 - July 24, 2002 STRAP OPTION 3.1.5. CPUCLK/HCKL PROGRAMMING ; MD[45] 1 0 MD[46] 0 1 Description HCLK between 33MHz and 64MHz HCLK between 64MHz and 133MHz DESKEW All other settings are reserved Table 3-1. Note that these straps are not accessible by software. Issue 1.0 - July 24, 2002 39/111 STRAP OPTION 3.2. TYPICAL STRAP OPTION IMPLEMENTATION Table Table 3-1.shows the detailed Strap options required to boot the STPC in ISA mode with a Actual Description Settings 2 MD1 Reserved Pull Up MD2 Pull down HCLK Speed HCLK = 66MHz MD3 Pull down PCI_CLKO Divisor Pull up PCICLK = HCLK/2 MD[4] MCLK Synchro (see Section 3.1.1. ) Pull down Asynchronous MD[5] Pull up MD[6] PCICLK PLL Window = PCI_CLKO Programming 32MHz - 64MHz Pull down MD[7] Pull down MD[8] ISA / PCMCIA / Local Bus ISA Mode Pull down MD[9] MD10 Reserved2 Pull down MD11 Reserved2 Pull down MD14 CPU clock Multiplication Pull up X2 Mode MD15 Reserved2 Pull up MD16 Reserved2 Pull up MD17 PCI_CLKO Divisor Pull up PCICLK = HCLK/2 MD18 HCLK Pad Direction Pull up Output MD19 MCLK Pad Direction Pull up Output MD20 DCLK Pad Direction Pull up Output MD21 Reserved2 Pull up MD23 Reserved2 Pull up MD24 Pull up MD25 HCLK PLL Speed Pull up HCLK = 66MHz MD26 Pull down MD27 Reserved2 Pull up MD28 Reserved2 Pull up MD29 Reserved2 Pull up MD30 Reserved2 Pull up MD31 Reserved2 Pull up MD32 Reserved2 Pull down MD33 Reserved2 Pull up MD34 Reserved2 Pull down MD35 Reserved2 Pull down MD36 Local Bus Boot Device Size User defined Not Applicable MD37 Reserved2 Pull down MD38 Reserved2 Pull down MD40 CPU clock Multiplication Pull up X2 mode MD41 Reserved2 Pull down MD42 Reserved2 Pull up MD 43 Reserved2 Pull down Note1: Strap options on TC/PA[3] and DACK_ENC[2:0]/PA[2:0] are required for all the STPC Atlas Configurations (ISA, PCMCIA, Local Bus). Note2: Must be implemented. Signal Designation Host Clock Frequency of 66MHz in X2 mode with internal keyboard/mouse, UARTS and parallel port enabled. Table 3-1. Typical Strap Option Implementation 40/111 Issue 1.0 - July 24, 2002 STRAP OPTION Actual Description Settings MD 45 Pull down HCLK between 64MHz and CPUCLK/HCKL Deskew Programming 133MHz MD 46 Pull up MD 47 Reserved2 Pull down MD 48 Reserved2 Pull up MD 50 Internal UART2 (see Section 3.1.4. ) Pull up Enable MD 51 Internal UART1 (see Section 3.1.4. ) Pull up Enable MD 52 Internal Kbd / Mouse (see Section 3.1.4. ) Pull up Enable MD 53 Internal Parallel Port (see Section 3.1.4. ) Pull up Enable TC1 Reserved2 Pull up 1 DACK_ENC[2] Reserved2 Pull up DACK_ENC[1]1 Reserved2 Pull up DACK_ENC[0]1 Reserved2 Pull up 1: Strap options on TC/PA[3] and DACK_ENC[2:0]/PA[2:0] are required for all the STPC Atlas Configurations (ISA, Note PCMCIA, Local Bus). Note2: Must be implemented. Signal Designation Table 3-1. Typical Strap Option Implementation Issue 1.0 - July 24, 2002 41/111 STRAP OPTION 42/111 Issue 1.0 - July 24, 2002 ELECTRICAL SPECIFICATIONS 4. ELECTRICAL SPECIFICATIONS 4.1. INTRODUCTION The electrical specifications in this chapter are valid for the STPC Atlas. 4.2. ELECTRICAL CONNECTIONS 4.2.3. RESERVED DESIGNATED PINS Pins designated as reserved should be left disconnected. Connecting a reserved pin to a pull-up resistor, pull-down resistor, or an active signal could cause unexpected results and possible circuit malfunctions. 4.3. ABSOLUTE MAXIMUM RATINGS The following table lists the absolute maximum ratings for the STPC Atlas device. Stresses beyond those listed under Table 4-1 limits may cause permanent damage to the device. These are stress ratings only and do not imply that operation under any conditions other than those specified in section "Operating Conditions". Exposure to conditions beyond those outlined in Table 4-1 may (1) reduce device reliability and (2) result in premature failure even when there is no immediately apparent sign of failure. Prolonged exposure to conditions at or near the absolute maximum ratings (Table 4-1) may also result in reduced useful life and reliability. 4.2.1. POWER/GROUND DECOUPLING CONNECTIONS/ Due to the high frequency of operation of the STPC Atlas, it is necessary to install and test this device using standard high frequency techniques. The high clock frequencies used in the STPC Atlas and its output buffer circuits can cause transient power surges when several output buffers switch output levels simultaneously. These effects can be minimized by filtering the DC power leads with low-inductance decoupling capacitors, using low impedance wiring, and by utilizing all of the VSS and VDD pins. 4.2.2. UNUSED INPUT PINS No unused input pin should be left unconnected unless they have an integrated pull-up or pulldown. Connect active-low inputs to VDD through a 20 k (10%) pull-up resistor and active-high inputs to VSS. For bi-directionnal active-high inputs, connect to VSS through a 20 k (10%) pull-up resistor to prevent spurious operation. 4.3.1. 5V TOLERANCE The STPC is capable of running with I/O systems that operate at 5 V such as PCI and ISA devices. Certain pins of the STPC tolerate inputs up to 5.5 V. Above this limit the component is likely to sustain permanent damage. All 5 volt tolerant pins are outlined in Table 2-3 Buffer Type Descriptions. Table 4-1. Absolute Maximum Ratings Symbol VDDx VCORE VI, VO V5T VESD TSTG TOPER PTOT Parameter DC Supply Voltage DC Supply Voltage for Core Digital Input and Output Voltage 5Volt Tolerance ESD Capacity (Human body mode) Storage Temperature Operating Temperature (Note 1) Maximum Power Dissipation (package) Minimum -0.3 -0.3 -0.3 -0.3 -40 0 -40 Maximum 4.0 2.7 VDD + 0.3 5.5 2000 +150 +85 +115 4.8 Units V V V V V C C C W Note 1: The figures specified apply to the Tcase of a STPC device that is soldered to a board, as detailed in the Design Guidelines Section, for Commercial and Industrial temperature ranges. Issue 1.0 - July 24, 2002 43/111 ELECTRICAL SPECIFICATIONS 4.4. DC CHARACTERISTICS Table 4-2. DC Characteristics Symbol VDD VCORE PDD PCORE Unit V V 3.0V < VDD < 3.6V W 2.45V < VCORE < 2.7V W Except XTALI -0.3 V Input Low Voltage VIL XTALI -0.3 V V Except XTALI 2.1 Input High Voltage VIH XTALI 2.35 V ILK Input Leakage Current Input, I/O -5 A Integrated Pull up/down 50 K Note 1; Power consumption is heavily dependant on the clock frequencies and on the enabled features. See details in Table 4-5 to Table 4-8. Parameter 3.3V Operating Voltage 2.5V Operating Voltage 3.3V Supply Power 2.5V Supply Power1 Test conditions Min 3.0 2.45 Typ 3.3 2.5 Max 3.6 2.7 0.24 4.1 0.8 0.8 VDD+0.3 VDD+0.3 5 Table 4-3. PAD buffers DC Characteristics I/O VIH min VIL max VOH min VOL max IOL min IOH max Cload max Derating (V) (V) (V) (V) (mA) (mA) (pF) (ps/pF)1 count ANA 10 2.35 0.9 OSCI13B 2 2.1 0.8 2.4 0.4 2 -2 50 BT4CRP 1 0.85*VDD 0.4 4 -4 100 30 BT8TRP_TC 7 2.4 0.4 8 -8 200 21 BD4STRP_FT 64 2 0.8 2.4 0.4 4 -4 100 42 BD4STRUP_FT 14 2 0.8 2.4 0.4 4 -4 100 41 BD4STRP_TC 26 2 0.8 2.4 0.4 4 -4 100 42 BD8STRP_FT 30 2 0.8 2.4 0.4 8 -8 200 23 BD8STRUP_FT 47 2 0.8 2.4 0.4 8 -8 200 23 BD8STRP_TC 12 2 0.8 2.4 0.4 8 -8 200 21 BD8TRP_TC 53 2 0.8 2.4 0.4 8 -8 200 21 BD8PCIARP_FT 50 0.5*VDD 0.3*VDD 0.9*VDD 0.1*VDD 1.5 - 0.5 200 15 BD14STARP_FT 18 2 0.8 2.4 0.4 14 -14 100 71 BD16STARUQP_TC 19 2 0.8 2.4 0.4 16 -16 400 12 SCHMITT_FT 1 2 0.8 TLCHT_FT 16 2 0.8 TLCHT_TC 1 2 0.8 TLCHTD_TC 1 2 0.8 TLCHTU_TC 1 2 0.8 USBDS_2V5 (slow) 45.2 4 2 0.8 2.4 0.4 100 USBDS_2V5 (fast) 98.8 Note 1: time to output variation depending on the capacitive load. Buffer Type CIN (pF) 5.61 6.89 5.97 5.97 5.83 5.96 5.96 7.02 7.03 6.97 6.20 9.34 5.97 5.97 5.97 5.97 5.97 8.41 Table 4-4. RAMDAC DC Specification Symbol Vref_dac INL DNL BLC Parameter Voltage Reference Integrated Non Linear Error Differentiated Non Linear Error Black Level Current Min 1.00 V 1.0 mA Max 1.24 V 3 LSB 1 LSB 2.0 mA 44/111 Issue 1.0 - July 24, 2002 ELECTRICAL SPECIFICATIONS Table 4-4. RAMDAC DC Specification Symbol WLC Parameter White Level Current Min 15.00 mA Max 18.50 mA Table 4-5. VGA RAMDAC Power Consumption DCLK (MHz) 6.25 - 135 DAC mode (State) Shutdown Active PMax (mW) VDD_DAC = 2.45V VDD_DAC = 2.7V 0 0 150 180 Table 4-6. 2.5V Power Consumptions (VCORE + VDD_x_PLL + VDD_DAC) HCLK (MHz) 66 CPUCLK (MHz) 133 (x2) MCLK (MHz) 66 Mode DCLK (MHz) Stopped SYNC 135 Stopped 66 133 (x2) 90 ASYNC 135 PMU (State) Stop Clock Full Speed Stop Clock Full Speed Stop Clock Full Speed Stop Clock Full Speed PMax (W) V2.5V=2.45V V2.5V=2.7V 1.5 1.9 2.5 3.0 2.1 2.6 2.1 3.6 1.9 2.4 2.8 3.5 2.5 3.1 3.3 4.1 Note 1: PCI clock at 33MHz Table 4-7. 3.3V Power Consumptions (VDD) HCLK (MHz) 66 66 CPUCLK (MHz) 133 (x2) 133 (x2) MCLK (MHz) 66 90 DCLK (MHz) 6.26 135 6.26 135 PMU (State) Full Speed Full Speed PMax (mW) 130 215 150 240 Table 4-8. PLL Power Consumptions PLL name VDD_DCLK_PLL VDD_DEVCLK_PLL VDD_HCLKI_PLL VDD_HCLKO_PLL VDD_MCLKI_PLL VDD_MCLKO_PLL VDD_PCICLK_PLL PMax (mW) VDD_PLL = 2.7V VDD_PLL = 2.45V 5 10 5 10 5 10 5 10 5 10 5 10 5 10 Issue 1.0 - July 24, 2002 45/111 ELECTRICAL SPECIFICATIONS 4.5. AC CHARACTERISTICS This section lists the AC characteristics of the STPC interfaces including output delays, input setup requirements, input hold requirements and output float delays. These measurements are based on the measurement points identified in Figure 4-1 and Figure 4-2. The rising clock edge reference level VREF and other reference levels are shown in Table 4-9 below. Input or output signals must cross these levels during testing. Figure 4-1 shows output delay (A and B) and input setup and hold times (C and D). Input setup and hold times (C and D) are specified minimums, defining the smallest acceptable sampling window a synchronous input signal must be stable for correct operation. Table 4-9. Drive Level and Measurement Points for Switching Characteristics Symbol VREF VIHD VILD Value 1.5 2.5 0.0 Units V V V Note: Refer to Figure 4-1. Figure 4-1. Drive Level and Measurement Points for Switching Characteristics Tx VIHD CLK: A B MIN VRef Valid Output n+1 MAX VRef VILD OUTPUTS: Valid Output n C D VIHD Valid Input INPUTS: VRef VILD LEGEND: A B C D - Maximum Output Delay Specification - Minimum Output Delay Specification - Minimum Input Setup Specification - Minimum Input Hold Specification 46/111 Issue 1.0 - July 24, 2002 ELECTRICAL SPECIFICATIONS Figure 4-2. CLK Timing Measurement Points T1 T2 VIH (MIN) VRef CLK VIL (MAX) T5 T3 T4 LEGEND: T1 - One Clock Cycle T2 - Minimum Time at VIH T3 - Minimum Time at VIL T4 - Clock Fall Time T5 - Clock Rise Time NOTE; All sIgnals are sampled on the rising edge of the CLK. Issue 1.0 - July 24, 2002 47/111 ELECTRICAL SPECIFICATIONS 4.5.1. POWER ON SEQUENCE Figure 4-3 describes the power-on sequence of the STPC, also called cold reset. There is no dependency between the different power supplies and there is no constraint on their rising time. Strap Options are continuously sampled during SYSRSTI# low and must remain stable. Once SYSRSTI# is high, they MUST NOT CHANGE until SYSRSTO# goes high. Bus activity starts only few clock cycles after the release of SYSRSTO#. The toggling signals depend on the STPC configuration. In ISA mode, activity is visible on PCI prior to the ISA bus as the controller is part of the south bridge. In Local Bus mode, the PCI bus is not accessed and the Flash Chip Select is the control signal to monitor. SYSRSTI# as no constraint on its rising edge but must stay active until power supplies are all within specifications, a margin of 10s is even recommended to let the STPC PLLs and strap options stabilize. Figure 4-3. Power-on timing diagram Power Supplies 14 M Hz > 10 us SYSRSTI# 1.6 V ISACLK VALID CONFIGURATION Strap Options HCLK PCI_CLK 2.3 m s SYSRSTO# 48/111 Issue 1.0 - July 24, 2002 ELECTRICAL SPECIFICATIONS 4.5.2 RESET SEQUENCE Figure 4-4 describes the reset sequence of the STPC, also called warm reset. The constraints on the strap options and the bus activities are the same as for the cold reset. The SYSRSTI# pulse duration must be long enough to have all the strap options stabilized and must be adjusted depending on resistor values. Figure 4-4. Reset timing diagram It is mandatory to have a clean reset pulse without glitches as the STPC could then sample invalid strap option setting and enter into an umpredictable mode. While SYSRSTI# is active, the PCI clock PLL runs in open loop mode at a speed of few 100's KHz. 14 M Hz SYSRSTI# ISACLK Strap Options HCLK PCI_CLK SYSRSTO# 2.3 m s M D[63:0] VALID CONFIGURATION 1.6 V Issue 1.0 - July 24, 2002 49/111 ELECTRICAL SPECIFICATIONS 4.5.3. SDRAM INTERFACE Figure 4-5, Table 4-10, Table 4-11 lists the AC characteristics of the SDRAM interface. The Figure 4-5. SDRAM Timing Diagram MCLKx clocks are the input clock of the SDRAM devices. MCLKx Tdelay MCLKI Thigh Tcycle STPC.output Toutput (max) Toutput (min) Tlow STPC.input Thold Tsetup Table 4-10. SDRAM Bus AC Timings - Commercial Temperature Range Parameter Min Typ MCLKI Cycle Time 10 MCLKI High Time 4 MCLKI Low Time 4 MCLKI Rising Time MCLKI Falling Time 2.1 Tdelay MCLKx to MCLKI delay 1.6 MCLKI to RAS# Valid 1.6 MCLKI to CAS# Valid 1.6 MCLKI to CS# Valid 1.35 MCLKI to DQM[ ] Outputs Valid Toutput 1.35 MCLKI to MD[ ] Outputs Valid 1.6 MCLKI to MA[ ] Outputs Valid 1.6 MCLKI to MWE# Valid 7.5 Tsetup MD[63:0] setup to MCKLI -0.36 Thold MD[63:0] hold from MCKLI Note: These timings are for a load of 50pF, part running at 100MHz and ReadCLK not activated Name Tcycle Thigh Tlow Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 5.2 5.2 5.2 5.2 5.2 5.2 5.2 The PC100 memory is recommended to reach 90MHz operation. 50/111 Issue 1.0 - July 24, 2002 ELECTRICAL SPECIFICATIONS Table 4-11. SDRAM Bus AC Timings - Industrial Temperature Range Parameter Min Typ MCLKI Cycle Time 11 MCLKI High Time 4 MCLKI Low Time 4 MCLKI Rising Time MCLKI Falling Time 1.8 Tdelay MCLKx to MCLKI delay 1.7 MCLKI to RAS# Valid 1.7 MCLKI to CAS# Valid 1.7 MCLKI to CS# Valid 2 MCLKI to DQM[ ] Outputs Valid Toutput 2 MCLKI to MD[ ] Outputs Valid 1.7 MCLKI to MA[ ] Outputs Valid 1.7 MCLKI to MWE# Valid 7.5 Tsetup MD[63:0] setup to MCKLI -0.36 Thold MD[63:0] hold from MCKLI Note: These timings are for a load of 50pF, part running at 90MHz and ReadCLK not activated Name Tcycle Thigh Tlow Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 6.5 6.5 6 6 7.8 6.5 6 The PC100 memory is recommended to reach 90MHz operation. Issue 1.0 - July 24, 2002 51/111 ELECTRICAL SPECIFICATIONS 4.5.4. PCI INTERFACE Figure 4-6 and Table 4-12 list the AC characteristics of the PCI interface. PCICLKx stands for any PCI device clock input. Figure 4-6. PCI Timing Diagram HCLK PCICLKx Tclkx PCICLKI Thigh Thclk Tcycle Tlow STPC.output Toutput (max) Toutput (min) STPC.input Thold Tsetup Table 4-12. PCI Bus AC Timings Parameter HCLK to PCICLKO delay (MD[30:27] = 1111) Thclk HCLK to PCICLKI delay Tclkx PCICLKI to PCICLKx skew Tcycle PCICLKI Cycle Time Thigh PCICLKI High Time Tlow PCICLKI Low Time PCICLKI Rising Time PCICLKI Falling Time PCICLKI to any output Setup to PCICLKI Hold from PCICLKI HCLK to any output Setup to HCLK Hold from HCLK Note: These timings are for a load of 50pF. Name Min 4.4 6.5 -0.5 30 13 13 Typ 5.0 7.5 0.3 Max 5.7 8.5 1.0 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.5 1.5 - 52/111 Issue 1.0 - July 24, 2002 ELECTRICAL SPECIFICATIONS 4.5.5 IPC INTERFACE Table 4-13 lists the AC characteristics of the IPC interface. Figure 4-7. IPC timing diagram ISACLK2X Tdly ISACLK Tsetup IRQ_MUX[3:0] Tsetup DREQ_MUX[1:0] Table 4-13. IPC Interface AC Timings Name Tdly Parameter ISACLK2X to ISACLK delay ISACLK2X to DACK_ENC[2:0] valid ISACLK2X to TC valid IRQ_MUX[3:0] Input setup to ISACLK2X DREQ_MUX[1:0] Input setup to ISACLK2X Min Max Unit nS nS nS nS nS Tsetup Tsetup 0 0 - Issue 1.0 - July 24, 2002 53/111 ELECTRICAL SPECIFICATIONS 4.5.6 ISA INTERFACE AC TIMING CHARACTERISTICS Table 4-8 and Table 4-14 list the AC characteristics of the ISA interface. Figure 4-8 ISA Cycle (ref Table 4-14) 2 15 38 37 14 13 12 9 18 ALE 22 AEN Valid AENx 34 33 LA [23:17] 3 Valid Address 42 11 24 41 10 SA [19:0] Valid Address, SBHE* 26 23 55 48 47 61 CONTROL (Note 1) IOCS16# MCS16# 54 IOCHRDY READ DATA WRITE DATA VALID DATA V.Data 64 58 59 28 57 27 25 56 29 Note 1: Stands for SMEMR#, SMEMW#, MEMR#, MEMW#, IOR# & IOW#. The clock has not been represented as it is dependent on the ISA Slave mode. Table 4-14. ISA Bus AC Timing Parameter LA[23:17] valid before ALE# negated LA[23:17] valid before MEMR#, MEMW# asserted 3a Memory access to 16-bit ISA Slave 3b Memory access to 8-bit ISA Slave 9 SA[19:0] & SBHE valid before ALE# negated 10 SA[19:0] & SBHE valid before MEMR#, MEMW# asserted 10a Memory access to 16-bit ISA Slave 10b Memory access to 8-bit ISA Slave 10 SA[19:0] & SHBE valid before SMEMR#, SMEMW# asserted 10c Memory access to 16-bit ISA Slave Note: The signal numbering refers to Table 4-8 Name 2 3 Min 5T 5T 5T 1T 2T 2T 2T Max Units Cycles Cycles Cycles Cycles Cycles Cycles Cycle 54/111 Issue 1.0 - July 24, 2002 ELECTRICAL SPECIFICATIONS Table 4-14. ISA Bus AC Timing Parameter Min 10d Memory access to 8-bit ISA Slave 2T 10e SA[19:0] & SBHE valid before IOR#, IOW# asserted 2T 11 ISACLK2X to IOW# valid 11a Memory access to 16-bit ISA Slave - 2BCLK 2T 11b Memory access to 16-bit ISA Slave - Standard 3BCLK 2T 11c Memory access to 16-bit ISA Slave - 4BCLK 2T 11d Memory access to 8-bit ISA Slave - 2BCLK 2T 11e Memory access to 8-bit ISA Slave - Standard 3BCLK 2T 12 ALE# asserted before ALE# negated 1T 13 ALE# asserted before MEMR#, MEMW# asserted 13a Memory Access to 16-bit ISA Slave 2T 13b Memory Access to 8-bit ISA Slave 2T 13 ALE# asserted before SMEMR#, SMEMW# asserted 13c Memory Access to 16-bit ISA Slave 2T 13d Memory Access to 8-bit ISA Slave 2T 13e ALE# asserted before IOR#, IOW# asserted 2T 14 ALE# asserted before AL[23:17] 14a Non compressed 15T 14b Compressed 15T 15 ALE# asserted before MEMR#, MEMW#, SMEMR#, SMEMW# negated 15a Memory Access to 16-bit ISA Slave- 4 BCLK 11T 15e Memory Access to 8-bit ISA Slave- Standard Cycle 11T 18a ALE# negated before LA[23:17] invalid (non compressed) 14T 18a ALE# negated before LA[23:17] invalid (compressed) 14T 22 MEMR#, MEMW# asserted before LA[23:17] 22a Memory access to 16-bit ISA Slave. 13T 22b Memory access to 8-bit ISA Slave. 13T 23 MEMR#, MEMW# asserted before MEMR#, MEMW# negated 23b Memory access to 16-bit ISA Slave Standard cycle 9T 23e Memory access to 8-bit ISA Slave Standard cycle 9T 23 SMEMR#, SMEMW# asserted before SMEMR#, SMEMW# negated 23h Memory access to 16-bit ISA Slave Standard cycle 9T 23l Memory access to 16-bit ISA Slave Standard cycle 9T 23 IOR#, IOW# asserted before IOR#, IOW# negated 23o Memory access to 16-bit ISA Slave Standard cycle 9T 23r Memory access to 8-bit ISA Slave Standard cycle 9T 24 MEMR#, MEMW# asserted before SA[19:0] 24b Memory access to 16-bit ISA Slave Standard cycle 10T 24d Memory access to 8-bit ISA Slave - 3BLCK 10T 24e Memory access to 8-bit ISA Slave Standard cycle 10T 24f Memory access to 8-bit ISA Slave - 7BCLK 10T 24 SMEMR#, SMEMW# asserted before SA[19:0] 24h Memory access to 16-bit ISA Slave Standard cycle 10T 24i Memory access to 16-bit ISA Slave - 4BCLK 10T 24k Memory access to 8-bit ISA Slave - 3BCLK 10T 24l Memory access to 8-bit ISA Slave Standard cycle 10T Table 4-8 Note: The signal numbering refers to Name Max Units Cycle Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Issue 1.0 - July 24, 2002 55/111 ELECTRICAL SPECIFICATIONS Table 4-14. ISA Bus AC Timing Parameter Min IOR#, IOW# asserted before SA[19:0] 24o I/O access to 16-bit ISA Slave Standard cycle 19T 24r I/O access to 16-bit ISA Slave Standard cycle 19T 25 MEMR#, MEMW# asserted before next ALE# asserted 25b Memory access to 16-bit ISA Slave Standard cycle 10T 25d Memory access to 8-bit ISA Slave Standard cycle 10T 25 SMEMR#, SMEMW# asserted before next ALE# asserted 25e Memory access to 16-bit ISA Slave - 2BCLK 10T 25f Memory access to 16-bit ISA Slave Standard cycle 10T 25h Memory access to 8-bit ISA Slave Standard cycle 10T 25 IOR#, IOW# asserted before next ALE# asserted 25i I/O access to 16-bit ISA Slave Standard cycle 10T 25k I/O access to 16-bit ISA Slave Standard cycle 10T 26 MEMR#, MEMW# asserted before next MEMR#, MEMW# asserted 26b Memory access to 16-bit ISA Slave Standard cycle 12T 26d Memory access to 8-bit ISA Slave Standard cycle 12T 26 SMEMR#, SMEMW# asserted before next SMEMR#, SMEMW# asserted 26f Memory access to 16-bit ISA Slave Standard cycle 12T 26h Memory access to 8-bit ISA Slave Standard cycle 12T 26 IOR#, IOW# asserted before next IOR#, IOW# asserted 26i I/O access to 16-bit ISA Slave Standard cycle 12T 26k I/O access to 8-bit ISA Slave Standard cycle 12T 28 Any command negated to MEMR#, SMEMR#, MEMR#, SMEMW# asserted 28a Memory access to 16-bit ISA Slave 3T 28b Memory access to 8-bit ISA Slave 3T 28 Any command negated to IOR#, IOW# asserted 28c I/O access to ISA Slave 3T 29a MEMR#, MEMW# negated before next ALE# asserted 1T 29b SMEMR#, SMEMW# negated before next ALE# asserted 1T 29c IOR#, IOW# negated before next ALE# asserted 1T 33 LA[23:17] valid to IOCHRDY negated 33a Memory access to 16-bit ISA Slave - 4 BCLK 8T 33b Memory access to 8-bit ISA Slave - 7 BCLK 14T 34 LA[23:17] valid to read data valid 34b Memory access to 16-bit ISA Slave Standard cycle 8T 34e Memory access to 8-bit ISA Slave Standard cycle 14T 37 ALE# asserted to IOCHRDY# negated 37a Memory access to 16-bit ISA Slave - 4 BCLK 6T 37b Memory access to 8-bit ISA Slave - 7 BCLK 12T 37c I/O access to 16-bit ISA Slave - 4 BCLK 6T 37d I/O access to 8-bit ISA Slave - 7 BCLK 12T 38 ALE# asserted to read data valid 38b Memory access to 16-bit ISA Slave Standard Cycle 4T 38e Memory access to 8-bit ISA Slave Standard Cycle 10T 38h I/O access to 16-bit ISA Slave Standard Cycle 4T 38l I/O access to 8-bit ISA Slave Standard Cycle 10T Note: The signal numbering refers to Table 4-8 Name 24 Max Units Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles 56/111 Issue 1.0 - July 24, 2002 ELECTRICAL SPECIFICATIONS Table 4-14. ISA Bus AC Timing Parameter Min Max SA[19:0] SBHE valid to IOCHRDY negated 41a Memory access to 16-bit ISA Slave 6T 41b Memory access to 8-bit ISA Slave 12T 41c I/O access to 16-bit ISA Slave 6T 41d I/O access to 8-bit ISA Slave 12T 42 SA[19:0] SBHE valid to read data valid 42b Memory access to 16-bit ISA Slave Standard cycle 4T 42e Memory access to 8-bit ISA Slave Standard cycle 10T 42h I/O access to 16-bit ISA Slave Standard cycle 4T 42l I/O access to 8-bit ISA Slave Standard cycle 10T 47 MEMR#, MEMW#, SMEMR#, SMEMW#, IOR#, IOW# asserted to IOCHRDY negated 47a Memory access to 16-bit ISA Slave 2T 47b Memory access to 8-bit ISA Slave 5T 47c I/O access to 16-bit ISA Slave 2T 47d I/O access to 8-bit ISA Slave 5T 48 MEMR#, SMEMR#, IOR# asserted to read data valid 48b Memory access to 16-bit ISA Slave Standard Cycle 2T 48e Memory access to 8-bit ISA Slave Standard Cycle 5T 48h I/O access to 16-bit ISA Slave Standard Cycle 2T 48l I/O access to 8-bit ISA Slave Standard Cycle 5T 54 IOCHRDY asserted to read data valid 54a Memory access to 16-bit ISA Slave 1T(R)/2T(W) 54b Memory access to 8-bit ISA Slave 1T(R)/2T(W) 54c I/O access to 16-bit ISA Slave 1T(R)/2T(W) 54d I/O access to 8-bit ISA Slave 1T(R)/2T(W) IOCHRDY asserted to MEMR#, MEMW#, SMEMR#, SMEMW#, 55a 1T IOR#, IOW# negated 55b IOCHRY asserted to MEMR#, SMEMR# negated (refresh) 1T 56 IOCHRDY asserted to next ALE# asserted 2T 57 IOCHRDY asserted to SA[19:0], SBHE invalid 2T 58 MEMR#, IOR#, SMEMR# negated to read data invalid 0T 59 MEMR#, IOR#, SMEMR# negated to data bus float 0T 61 Write data before MEMW# asserted 61a Memory access to 16-bit ISA Slave 2T Memory access to 8-bit ISA Slave (Byte copy at end of 61b 2T start) 61 Write data before SMEMW# asserted 61c Memory access to 16-bit ISA Slave 2T 61d Memory access to 8-bit ISA Slave 2T 61 Write Data valid before IOW# asserted 61e I/O access to 16-bit ISA Slave 2T 61f I/O access to 8-bit ISA Slave 2T 64a MEMW# negated to write data invalid - 16-bit 1T 64b MEMW# negated to write data invalid - 8-bit 1T 64c SMEMW# negated to write data invalid - 16-bit 1T 64d SMEMW# negated to write data invalid - 8-bit 1T Note: The signal numbering refers to Table 4-8 Name 41 Units Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Issue 1.0 - July 24, 2002 57/111 ELECTRICAL SPECIFICATIONS Table 4-14. ISA Bus AC Timing Parameter IOW# negated to write data invalid MEMW# negated to copy data float, 8-bit ISA Slave, odd Byte 64f by ISA Master IOW# negated to copy data float, 8-bit ISA Slave, odd Byte by 64g ISA Master Note: The signal numbering refers to Table 4-8 Name 64e Min 1T 1T 1T Max Units Cycles Cycles Cycles 58/111 Issue 1.0 - July 24, 2002 ELECTRICAL SPECIFICATIONS 4.5.7 LOCAL BUS INTERFACE Figure 4-3 to Figure 4-12 and Table 4-16 list the AC characteristics of the Local Bus interface. Figure 4-9. Synchronous Read Cycle HCLK PA[ ] bus Tsetup CSx# Tactive Thold BE#[1:0] PRD# PD[15:0] Figure 4-10. Asynchronous Read Cycle HCLK PA[ ] bus Tsetup CSx# Tend Thold BE#[1:0] PRD# PD[15:0] PRDY Issue 1.0 - July 24, 2002 59/111 ELECTRICAL SPECIFICATIONS Figure 4-11. Synchronous Write Cycle HCLK PA[ ] bus Tsetup CSx# Tactive Thold BE#[1:0] PWR# PD[15:0] Figure 4-12. Asynchronous Write Cycle HCLK PA[ ] bus Tsetup CSx# Tend Thold BE#[1:0] PWR# PD[15:0] PRDY 60/111 Issue 1.0 - July 24, 2002 ELECTRICAL SPECIFICATIONS The Table 4-15 below refers to Vh, Va, Vs which are the register value for Setup time, Active Time and Hold time, as described in the Programming Manual. Table 4-15. Local Bus cycle lenght Cycle Memory (FCSx#) Peripheral (IOCSx#) Tsetup 4 + Vh 4 + Vh Tactive 2 + Va 2 + Va Thold 4 + Vs 4 + Vs Tend 4 4 Unit HCLK HCLK Table 4-16. Local Bus Interface AC Timing Name Parameters HCLK to PA bus HCLK to PD bus HCLK to FCS#[1:0] HCLK to IOCS#[3:0] HCLK to PWR#, PRD# HCLK to BE#[1:0] PD[15:0] Input setup to HCLK PD[15:0] Input hold to HCLK PRDY Input setup to HCLK PRDY Input hold to HCLK Min 2 2 Max 15 15 15 15 15 15 4 4 Units nS nS nS nS nS nS nS nS nS nS Issue 1.0 - July 24, 2002 61/111 ELECTRICAL SPECIFICATIONS 4.5.8 PCMCIA INTERFACE Table 4-17 lists the AC characteristics of the PCMCIA interface. Table 4-17. PCMCIA Interface AC Timing Name t27 t28 t29 t30 t31 t32 t33 t34 t35 t36 t37 t38 Parameters Input setup to ISACLK2X Input hold from ISACLK2X ISACLK2X to IORD ISACLK2X to IORW ISACLK2X to AD[25:0] ISACLK2X to OE# ISACLK2X to WE# ISACLK2X to DATA[15:0] ISACLK2X to INPACK ISACLK2X to CE1# ISACLK2X to CE2# ISACLK2X to RESET Min 24 5 2 2 0 2 7 7 2 Max Units nS nS nS nS nS nS nS nS nS nS nS nS 55 55 25 55 55 35 55 65 65 55 62/111 Issue 1.0 - July 24, 2002 ELECTRICAL SPECIFICATIONS 4.5.9 IDE INTERFACE Figure 4-13, Figure 4-14 and Table 4-18 lists the AC characteristics of the IDE interface. Figure 4-13. IDE PIO timing diagram CS#,DA[2:0] Thold DIOR#,DIOW# Tsetup DD[15:0] IORDY Figure 4-14. IDE DMA timing diagram CS# REQ ACK# Thold DIOR#,DIOW# Tsetup DD[15:0] read DD[15:0] write Table 4-18. IDE Interface Timing Name Tsetup Thold Parameters DD[15:0] setup to PIOR#/SIOR# falling DD[15:0} hold to PIOR#/SIOR# falling Min 15 0 Max Units ns ns Issue 1.0 - July 24, 2002 63/111 ELECTRICAL SPECIFICATIONS 4.5.10 VGA INTERFACE Table 4-19 lists the AC characteristics of the VGA interface. Table 4-19. Graphics Adapter (VGA) AC Timing Name Parameter DCLK (input) Cycle Time DCLK (input) High Time DCLK (input) Low Time DCLK (input) Rising Time DCLK (input) Falling Time DCLK (input) to R,G,B valid DCLK (input) to HSYNC valid DCLK (input) to VSYNC valid DCLK (input) to COL_SEL valid DCLK (output) Cycle Time DCLK (output) High Time DCLK (output) Low Time DCLK (output) to R,G,B valid DCLK (output) to HSYNC valid DCLK (output) to VSYNC valid DCLK (output) to COL_SEL valid Min Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4.5.11 TFT INTERFACE Table 4-20 lists the AC characteristics of the TFT interface. Table 4-20. TFT Interface Timings Name Parameters DCLK (input) to R[5:0], G[5:0], B[5;0] DCLK (input) to FPLINE DCLK (input) to FPFRAME DCLK (output) to R[5:0], G[5:0], B[5;0] DCLK (output) to FPLINE DCLK (output) to FPFRAME Min Max Units nS nS nS nS nS nS 15 15 15 64/111 Issue 1.0 - July 24, 2002 ELECTRICAL SPECIFICATIONS 4.5.12 VIDEO INPUT PORT Table 4-21 lists the AC characteristics of the VIP interface. Table 4-21. Video Input AC Timings Name Parameter VCLK Cycle Time VCLK High Time VCLK Low Time VCLK Rising Time VCLK Falling Time VIN[7:0] setup to VCLK VIN[7:0] hold from VCLK ODD_EVEN setup to VCLK ODD_EVEN hold from VCLK VCS setup to VCLK VCS hold from VCLK Min Max Unit ns ns ns ns ns ns ns ns ns ns ns Issue 1.0 - July 24, 2002 65/111 ELECTRICAL SPECIFICATIONS 4.5.13 USB INTERFACE The USB interface integrated into the STPC device is compliant with the USB 1.1 standard. 4.5.14 KEYBOARD & MOUSE INTERFACES Table 4-22 and Table 4-23 list the AC characteristics of the Keyboard and Mouse interfaces. Table 4-22. Keyboard Interface AC Timing Name Parameters Input setup to KBCLK Input hold to KBCLK KBCLK to KBDATA Min 5 1 Max 12 Units nS nS nS Table 4-23. Mouse Interface AC Timing Name Parameters Input setup to MCLK Input hold to MCLK MCLK to MDATA Min 5 1 Max 12 Units nS nS nS 4.5.15 IEEE1284 INTERFACE Table 4-24 lists the AC characteristics of the Keyboard and Mouse interfaces. Table 4-24. Parallel Interface AC Timing Name Parameters STROBE# to BUSY setup PD bus to AUTPFD# hold PB bus to BUSY setup Min 0 0 0 Max Units nS nS nS 66/111 Issue 1.0 - July 24, 2002 ELECTRICAL SPECIFICATIONS 4.5.16 JTAG INTERFACE Figure 4-15 and Table 4-21 list characteristics of the JTAG interface. the AC Figure 4-15. JTAG timing diagram Treset TRST Tcycle TCK TMS,TDI Tjset TDO Tjout STPC.input Tpset STPC.output Tpout Tphld Tjhld Table 4-25. JTAG AC Timings Name Treset Tcycle Parameter TRST pulse width TCLK period TCLK rising time TCLK falling time TMS setup time TMS hold time TDI setup time TDI hold time TCLK to TDO valid STPC pin setup time STPC pin hold time TCLK to STPC pin valid Min 1 400 Max Unit Tcycle ns ns ns ns ns ns ns ns ns ns ns 20 20 200 200 200 200 30 30 30 30 Tjset Tjhld Tjset Tjhld Tjout Tpset Tphld Tpout Issue 1.0 - July 24, 2002 67/111 ELECTRICAL SPECIFICATIONS 4.5.17 INTENSIONNALLY BLANK 68/111 Issue 1.0 - July 24, 2002 MECHANICAL DATA 5. MECHANICAL DATA 5.1. 516-PIN PACKAGE DIMENSION The pin numbering for the STPC 516-pin Plastic BGA package is shown in Figure 5-1. Figure 5-1. 516-Pin PBGA Package - Top View Dimensions are shown in Figure 5-2, Table 5-1 and Figure 5-3, Table 5-2. 1 2 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Issue 1.0 - July 24, 2002 69/111 MECHANICAL DATA Figure 5-2. 516-pin PBGA Package - PCB Dimensions A1 Ball Pad Corner A B A E F D Detail CG Table 5-1. 516-pin PBGA Package - PCB Dimensions Symbols A B C D E F G Min 34.80 1.22 0.60 1.57 0.15 0.05 0.75 mm Typ 35.00 1.27 0.76 1.62 0.20 0.10 0.80 Max 35.20 1.32 0.90 1.67 0.25 0.15 0.85 Min 1.370 0.048 0.024 0.062 0.006 0.002 0.030 inches Typ 1.378 0.050 0.030 0.064 0.008 0.004 0.032 Max 1.386 0.052 0.035 0.066 0.001 0.006 0.034 70/111 Issue 1.0 - July 24, 2002 MECHANICAL DATA Figure 5-3. 516-pin PBGA Package - Dimensions C F D E Solderball Solderball after collapse B A G Table 5-2. 516-pin PBGA Package - Dimensions Symbols A B C D E F G Min 0.50 1.12 0.60 0.52 0.63 0.60 mm Typ 0.56 1.17 0.76 0.53 0.78 0.63 30.0 Max 0.62 1.22 0.92 0.54 0.93 0.66 Min 0.020 0.044 0.024 0.020 0.025 0.024 inches Typ 0.022 0.046 0.030 0.021 0.031 0.025 11.8 Max 0.024 0.048 0.036 0.022 0.037 0.026 Issue 1.0 - July 24, 2002 71/111 MECHANICAL DATA 5.2. 516-PIN PACKAGE THERMAL DATA 516-pin PBGA package has a Power Dissipation Capability of 4.5W which increases to 6W when used with a Heatsink. The structure in shown in Figure 5-4. Thermal dissipation options are illustrated in Figure 5-5 and Figure 5-6. Figure 5-4. 516-Pin PBGA Structure Signal layers Power & Ground layers Thermal balls Figure 5-5. Thermal Dissipation Without Heatsink Board Ambient Rca Case Rjc Junction Rjb Board Rba Ambient Board 8.5 6 Junction Board dimensions: - 10.2 cm x 12.7 cm - 4 layers (2 for signals, 1 GND, 1VCC) 6 Case 125 The PBGA is centred on board There are no other devices 1 via pad per ground ball (8-mil wire) 40% copper on signal layers Copper thickness: - 17m for internal layers - 34m for external layers Airflow = 0 Board temperature taken at the centre balls Ambient Rja = 13 C/W 72/111 Issue 1.0 - July 24, 2002 MECHANICAL DATA Figure 5-6. Thermal Dissipation With Heatsink Board Ambient Rca Case Rjc Junction Rjb Board Rba Ambient Board 8.5 3 Junction Board dimensions: - 10.2 cm x 12.7 cm - 4 layers (2 for signals, 1 GND, 1VCC) 6 Case 50 The PBGA is centred on board There are no other devices 1 via pad per ground ball (8-mil wire) 40% copper on signal layers Copper thickness: - 17m for internal layers - 34m for external layers Airflow = 0 Board temperature taken at the centre balls Heat sink is 11.1C/W Ambient Rja = 9.5 C/W Issue 1.0 - July 24, 2002 73/111 MECHANICAL DATA 5.3. SOLDERING RECOMMENDATIONS High quality, low defect soldering requires identifying the optimum temperature profile for reflowing the solder paste, therefore optimizing the process. The heating and cooling rise rates must be compatible with the solder paste and components. A typical profile consists of a preheat, dryout, reflow and cooling sections. The most critical parameter in the preheat section is to minimize the rate of temperature rise to less than 2C / second, in order to minimize thermal shock on the semi-conductor components. Dryout section is used primarily to ensure that the solder paste is fully dried before hitting reflow temperatures. Solder reflow is accomplished in the reflow zone, where the solder paste is elevated to a temperature greater than the melting point of the solder. Melting temperature must be exceeded by approximately 20C to ensure quality reflow. In reality the profile is not a line, but rather a range of temperatures all solder joints must be exposed. The total temperature deviation from component thermal mismatch, oven loading and oven uniformity must be within the band. Figure 5-7. Reflow soldering temperature range Temperature ( C ) 250 200 150 100 50 PREHEAT 0 DRYOUT REFLOW 240 COOLING 0 Time ( s ) 74/111 Issue 1.0 - July 24, 2002 DESIGN GUIDELINES 6. DESIGN GUIDELINES 6.1. TYPICAL APPLICATIONS The STPC Atlas is well suited for many applications. Some of the possible implementations are described below. These protocols have room for dedicated data channels in case the terminal is not 'thin' and can execute locally some applications, hence optimizing the bandwidth usage. For example, if a terminal has browsing or MPEG decoding capability, the server will provide internet source files or MPEG streaming. The same hardware can run X-terminal protocol and can be reconfigured by the server when booting on the network by uploading a different OS and application. 6.1.1. THIN CLIENT A Thin-Client is a terminal running ICATM (Citrix) or RDPTM (Microsoft) protocol. The display is computed by the server and sent in a compressed way to the terminal for display. The same streaming approach is used for sending the keyboard/mouse/USB data to the server. Figure 6-1. Thin-Client - Block Diagram SDRAM 64 VGA 16 TFT FLASH LAN PCI MPEG DECODER STPC ATLAS USB CCIR IEEE1284 AUDIO IDE / PCI Kbd / Mouse Issue 1.0 - July 24, 2002 75/111 DESIGN GUIDELINES 6.1.2. INTERNET TERMINAL The internet terminal described here is an optimized implementation where the STPC Atlas board is integrated into the CRT itself. The advantages are a reduced overall cost and a good image definition. The STPC Atlas platform being integrated into the monitor itself enables the choice of a limited amount of horizontal frequencies and simplifies the CRT driving stage: - 1024x768: 56.5KHz horizontal, 70Hz vertical - 800x600: 53.7KHz horizontal, 85Hz vertical Like for the Thin-Client, an external MPEG decoder can be connected to the STPC Atlas through the PCI bus and the Video Input Port. The same concept can be applied using a TFT display instead of a CRT. Figure 6-2. Internet Terminal - Block Diagram SDRAM VSYNC 64 VBOOSTER YOKE FLASH 16 HSYNC MODEM SmartCard AUDIO USB PCI RS232 IDE / PCI STPC ATLAS R,G,B 3 E2 PROM GPIOs I 2C KEYSEL KEY+ QUAD DAC STV2001 H YOKE R,G,B 3 TDA9535 3 DC RESTORING 3 3 IEEE1284 Kbd / Mouse TILT 76/111 Issue 1.0 - July 24, 2002 DESIGN GUIDELINES 6.2. STPC CONFIGURATION The STPC is a very flexible product thanks to decoupled clock domains and to strap options enabling a user-optimized configuration. As some trade off are often necessary, it is important to do an analysis of the application needs prior to design a system based on this product. The applicative constraints are usually the following: - CPU performance - graphics / video performances - power consumption - PCI bandwidth - booting time - EMC Some other elements can help to tune the choice: - Code size of CPU Consuming tasks - Data size and location On the STPC side, the configurable parameters are the following: - synchronous / asynchronous mode - HCLK speed - MCLK speed - Local Bus / ISA bus C 1 2 Table 6-2. Main STPC modes Mode Synchronous Asynchronous HCLK MHz 66 66 CPU clock clock ratio 133 (x2) 133 (x2) MCLK MHz 66 90 The advantage of the synchronous mode compared to the asynchronous mode is a lower latency when accessing SDRAM from the CPU or the PCI (saves 4 MCLK cycles for the first access of the burst). For the same CPU to Memory transfer performance, MCLK has to be roughly higher by 20MHz between SYNC and ASYNC modes to get the same system performance level (example: 66MHz SYNC = 86MHz ASYNC) . In all cases, use SDRAM with CAS Latency equals to 2 (CL2) for the best performances. The advantage of the asynchronous mode is the capability to reprogram the MCLK speed on the fly. This could help for applications where power consumption must be optimized. The last, and more complex, information to consider is the behaviour of the software. In case high CPU or FPU computation is needed, it is sometime better to be in DX2-133/MCLK=66 synchronous mode than DX2-133/MCLK=90 asynchronous mode. This depends on the locality of the number crunching code and the amount of data manipulated. The Table 6-3 below gives some examples. The right column correspond to the configuration number as described in Table 6-2: Table 6-3. Clock mode selection Constraints Need CPU power Critical code fits into L1 cache Need CPU power Code or data does not fit into L1 cache Need high PCI bandwitdh Need flexible SDRAM speed C 1 3 3 2 6.2.1. LOCAL BUS / ISA BUS The selection between the ISA bus and the Local Bus is relatively simple. The first one is a standard bus but slow. The Local Bus is fast and programmable but doesn't support any DMA nor external master mechanisms. The Table 6-1 below summarize the selection: Table 6-1. Bus mode selection Need Legacy I/O device (Floppy, ...), Super I/O DMA capability (Soundblaster) Flash, SRAM, basic I/O device Fast boot Boot flash of 4MB or more Programmable Chip Select Selection ISA Bus ISA Bus Local Bus Local Bus Local Bus Local Bus Before implementing a function requiring DMA capability on the ISA bus, it is recommended to check if it exists on PCI, or if it can be implemented differently, in order to use the local bus mode. Obviously, the values for HCLK or MCLK can be reduced compared to Table 6-2 in case there is no need to push the device at its limits, or when avoiding to use specific frequency ranges (FM radio band for example). 6.3. ARCHITECTURE RECOMMENDATIONS This section describes the recommend implementations for the STPC interfaces. For more details, download the Reference Schematics from the STPC web site. 6.2.2. CLOCK CONFIGURATION The CPU clock and the memory clock are independent unless the "synchronous mode" strap option is set (see the STRAP OPTIONS chapter). The potential clock configurations are then relatively limited as listed in Table 6-2. Issue 1.0 - July 24, 2002 77/111 DESIGN GUIDELINES 6.3.1. POWER DECOUPLING An appropriate decoupling of the various STPC power pins is mandatory for optimum behaviour. When insufficient, the integrity of the signals is deteriorated, the stability of the system is reduced and EMC is increased. minimum. The use of multiple capacitances with values in decade is the best (for example: 10pF, 1nF, 100nF, 10uF), the smallest value, the closest to the power pin. Connecting the various digital power planes through capacitances will reduce furthermore the overall impedance and electrical noise. 6.3.1.1. PLL decoupling This is the most important as the STPC clocks are generated from a single 14MHz stage using multiple PLLs which are highly sensitive analog cells. The frequencies to filter are the 25-50 KHz range which correspond to the internal loop bandwidth of the PLL and the 10 to 100 MHz frequency of the output. PLL power pins can be tied together to simplify the board layout. Figure 6-3. PLL decoupling PWR 6.3.2. 14MHZ OSCILLATOR STAGE The 14.31818 MHz oscillator stage can be implemented using a quartz, which is the preferred and cheaper solution, or using an external 3.3V oscillator. The crystal must be used in its series-cut fundamental mode and not in overtone mode. It must have an Equivalent Series Resistance (ESR, sometimes referred to as Rm) of less than 50 Ohms (typically 8 Ohms) and a shunt capacitance (Co) of less than 7 pF. The balance capacitors of 16 pF must be added, one connected to each pin, as described in Figure 6-4. In the event of an external oscillator providing the master clock signal to the STPC Atlas device, the LVTTL signal should be connected to XTALI, as described in Figure 6-4. As this clock is the reference for all the other onstrongly chip generated clocks, it is recommended to shield this stage, including the 2 wires going to the STPC balls, in order to reduce the jitter to the minimum and reach the optimum system stability. VDD_PLL 100nF 47uF VSS_PLL GND Connections must be as short as possible 6.3.1.2. Decoupling of 3.3V and Vcore A power plane for each of these supplies with one decoupling capacitance for each power pin is the Figure 6-4. 14.31818 MHz stage XTALI XTALO XTALI XTALO 3.3V 15pF 15pF 78/111 Issue 1.0 - July 24, 2002 DESIGN GUIDELINES 6.3.3. SDRAM The STPC provides all the signals for SDRAM control. Up to 128 MBytes of main memory are supported. All Banks must be 64 bits wide. Up to 4 memory banks are available when using 16Mbit devices. Only up to 2 banks can be connected when using 64Mbit and 128Mbit components due to the reallocation of CS2# and CS3# signals. This is described in Table 6-4 and Table 6-5. Graphics memory resides at the beginning of Bank 0. Host memory begins at the top of graphics memory and extends to the top of populated SDRAM. Bank 0 must always be populated. Figure 6-5, Figure 6-6 and Figure 6-7 show some typical implementations. The purpose of the serial resistors is to reduce signal oscillation and EMI by filtering line reflections. The capacitance in Figure 6-5 has a filtering effect too, while it is used for propagation delay compensation in the 2 other figures. Figure 6-5. One Memory Bank with 4 Chips (16-bit) MCLKI Length(MCLKI) = Length(MCLKy) with y = {A,B,C,D} MCLKO 10pF CS0# MA[12:0] BA[1:0] RAS0# CAS0# WE# DQM[7:0] MD[63:0] Reference Knot MCLKD MCLKC MCLKB MCLKA DQM[7:6] MD[63:48] DQM[5:4] MD[47:32] DQM[3:2] MD[31:16] DQM[1:0] MD[15:0] Issue 1.0 - July 24, 2002 79/111 DESIGN GUIDELINES Figure 6-6. One Memory Banks with 8 Chips (8-bit) MCLKI 10pF Length(MCLKI) = Length(MCLKy) with y = {A,B,C,D,E,F,G,H} MCLKO CY2305 CS0# MA[12:0] BA[1:0] RAS0# CAS0# WE# DQM[7:0] MD[63:0] H G F E D C B A DQM[7] MD[63:56] DQM[1] DQM[0] MD[15:8] MD[7:0] Figure 6-7. Two Memory Banks with 8 Chips (8-bit) MCLKI 22pF Length(MCLKI) = Length(MCLKyx) with y = {A,B,C,D,E,F,G,H} x = {0,1} MCLKO CY2305 CS1# CS0# MA[12:0] BA[1:0] RAS0# CAS0# WE# DQM[7:0] MD[63:0] H0 H 1 G0 G1 F 0 F1 E0 E1 D0 D1 C0 C1 B0 B1 A0 A1 DQM[7] MD[63:56] DQM[1] DQM[0] MD[15:8] MD[7:0] 80/111 Issue 1.0 - July 24, 2002 DESIGN GUIDELINES For other implementations like 32-bit SDRAM devices, refers to the SDRAM controller signal multiplexing and address mapping described in the following Table 6-4 and Table 6-5. Table 6-4. DIMM Pinout SDRAM Density Internal Banks DIMM Pin Number ... 123 126 39 122 16 Mbit 2 Banks MA[10:0] BA0 (MA11) 64/128 Mbit 2 Banks MA[10:0] MA11 MA12 BA0 (MA13) 64/128 Mbit 4 Banks MA[10:0] MA11 BA1 (MA12) BA0 (MA13) STPC I/F MA[10:0] CS2# (MA11) CS3# (MA12) CS3# (BA1) BA0 Table 6-5. Address Mapping Address Mapping: 16 Mbit - 2 internal banks STPC I/F BA0 MA10 MA9 RAS Address A11 A22 A21 CAS Address A11 0 A24 Address Mapping: 64/128 Mbit - 2 internal banks STPC I/F BA0 MA12 MA11 MA10 MA9 RAS Address A11 A24 A23 A22 A21 CAS Address A11 0 0 0 A26 Address Mapping: 64/128 Mbit - 4 internal banks STPC I/F BA0 BA1 MA11 MA10 MA9 RAS Address A11 A12 A24 A23 A22 CAS Address A11 A12 0 0 A26 MA8 A2 A23 MA8 A20 A25 MA8 A21 A25 MA7 A19 A10 MA7 A19 A10 MA7 A20 A10 MA6 A18 A9 MA6 A18 A9 MA6 A19 A9 MA5 A17 A8 MA5 A17 A8 MA5 A18 A8 MA4 A16 A7 MA4 A16 A7 MA4 A17 A7 MA3 A15 A6 MA3 A15 A6 MA3 A16 A6 MA2 A14 A5 MA2 A14 A5 MA2 A15 A5 MA1 A13 A4 MA1 A13 A4 MA1 A14 A4 MA0 A12 A3 MA0 A12 A3 MA0 A13 A3 6.3.4. PCI BUS The PCI bus is always active and the following control signals must be pulled-up to 3.3V or 5V through 2K2 resistors even if this bus is not connected to an external device: FRAME#, TRDY#, IRDY#, STOP#, DEVSEL#, LOCK#, SERR#, PERR#, PCI_REQ#[2:0]. PCI_CLKO must be connected to PCI_CLKI through a 10 to 33 Ohms resistor. Figure 6-8 shows a typical implementation. For more information on layout constraints, go to the place and route recommendations section. Figure 6-8. Typical PCI clock routing PCICLKI 0 - 33pF PCICLKA PCICLKB PCICLKO 0 - 22 10 - 33 PCICLKC Device A Device B Device C Issue 1.0 - July 24, 2002 81/111 DESIGN GUIDELINES when implementing the delay on PCICLKI In the case of higher clock load it is recommended according to the PCI section of the Electrical to use a zero-delay clock buffer as described in Specifications chapter. Figure 6-9. This approach is also recommended Figure 6-9. PCI clock routing with zero-delay clock buffer PCICLKI PCICLKI PCICLKO PLL Device A Device B Device C Device D CY2305 PCICLKO PLL Device A Device B Device C Device D CY2305 Implementation 1 Implementation 2 82/111 Issue 1.0 - July 24, 2002 DESIGN GUIDELINES 6.3.5. LOCAL BUS The local bus has all the signals to directly connect flash devices or I/O devices. Figure 6-10 describes how to connect a 16-bit boot flash (the corresponding strap options must be set accordingly). Figure 6-10. Typical 16-bit boot flash implementation 3V3 PA[22:1] FCS0# PRD# PWR# PD[15:0] SYSRSTI# STPC 22 16 A[22:1] CE OE W DQ[15:0] RP B CLK RB LE R GND RESET# M58LW064A Issue 1.0 - July 24, 2002 83/111 DESIGN GUIDELINES 6.3.6. IPC When an interrupt line is used internally, the corresponding input can be grounded. In most of the embedded designs, only few interrupts lines are necessary and the glue logic can be simplified. Most of the IPC signals are multiplexed: Interrupt inputs, DMA Request inputs, DMA Acknowledge outputs. The figure below describes a complete implementation of the IRQ[15:0] time-multiplexing. Figure 6-11. Typical IRQ multiplexing 74x153 Timer 0 Keyboard Slave PIC COM2/COM4 COM1/COM3 LPT2 Floppy LPT1 IRQ[0] IRQ[1] IRQ[2] IRQ[3] IRQ[4] IRQ[5] IRQ[6] IRQ[7] 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 A B 1Y IRQ_MUX[0] 2Y IRQ_MUX[1] 1G 2G RTC Mouse FPU PCI / IDE PCI / IDE Floppy IRQ[8] IRQ[9] IRQ[10] IRQ[11] IRQ[12] IRQ[13] IRQ[14] IRQ[15] 74x153 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 A B 1Y IRQ_MUX[2] 2Y IRQ_MUX[3] ISA_CLK2X ISA_CLK 1G 2G When the interface is integrated into the STPC, the corresponding interrupt line can be grounded as it is connected internally. For example, if the integrated IDE controller is activated, the IRQ[14] and IRQ[15] inputs can be grounded. 84/111 Issue 1.0 - July 24, 2002 DESIGN GUIDELINES The figure below describes a complete implementation of the external glue logic for DMA Request time-multiplexing and DMA Acknowledge demultiplexing. Like for the interrupt lines, this logic can be simplified when only few DMA channels are used in the application. This glue logic is not needed in Local bus mode as it does not support DMA transfers. Figure 6-12. Typical DMA multiplexing and demultiplexing 74x153 ISA, Refresh ISA, PIO ISA, FDC ISA, PIO Slave DMAC ISA ISA ISA DRQ[0] DRQ[1] DRQ[2] DRQ[3] DRQ[4] DRQ[5] DRQ[6] DRQ[7] 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 A B 1Y DREQ_MUX[0] 2Y DREQ_MUX[1] 1G 2G ISA_CLK2X ISA_CLK 74x138 Y0# Y1# Y2# Y3# Y4# Y5# Y6# Y7# DACK0# DACK1# DACK2# DACK3# DACK5# DACK6# DACK7# DMA_ENC[0] DMA_ENC[1] DMA_ENC[2] A B C G1 G2A G2B Issue 1.0 - July 24, 2002 85/111 DESIGN GUIDELINES 6.3.7. IDE / ISA DYNAMIC DEMULTIPLEXING Some of the ISA bus signals are dynamically multiplexed to optimize the pin count. Figure 6-13 describes how to implement the external glue logic to demultiplex the IDE and ISA interfaces. In Local Bus mode the two buffers are not needed and the NAND gates can be simplified to inverters. Figure 6-13. Typical IDE / ISA Demultiplexing STPC bus / DD[15:0] MASTER# ISAOE# A B 74xx245 DIR OE RMRTCCS# KBCS# RTCRW# RTCDS SA[19:8] PCS1# PCS3# SCS1# SCS3# LA[22] LA[23] LA[24] LA[25] 6.3.8. BASIC AUDIO USING IDE INTERFACE When the application requires only basic audio capabilities, an audio DAC on the IDE interface can avoid using a PCI-based audio device. This low cost solution is not CPU consuming thanks to the DMA controller implemented in the IDE controller and can generate 16-bit stereo sound. The clock speed is programmable when using the speaker output. Figure 6-14. Basic audio on IDE DD[15:0] PCS1 PDIOW# PDRQ SYSRSTO# 16 * D[15:0] CS# WR# A/B Right Audio Out Left Vcc Vcc Stereo DAC PR D Speaker STPC PR Q D Q Q RST Q RST 74xx74 Vcc Note * : the inverter can be removed when the DAC CS# is directly connected to GND 86/111 Issue 1.0 - July 24, 2002 DESIGN GUIDELINES 6.3.9. VGA INTERFACE The STPC integrates a voltage reference and video buffers. The amount of external devices is then limited to the minimum as described in the Figure 6-15. All the resistors and capacitors have to be as close as possible to the STPC while the circuit protector DALC112S1 must be close to the VGA connector. The DDC[1:0] lines, not represented here, have also to be protected when they are used on the VGA connector. COL_SEL can be used when implementing the Picture-In-Picture function outside the STPC, for example when multiplexing an analog video source. In that case, the CRTC of the STPC has to be genlocked to this analog source. DCLK is usually used by the TFT display which has RGB inputs in order to synchronise the picture at the level of the pixel. When the VGA interface is not needed, the signals R, G, B, HSYNC, VSYNC, COMP, RSET can be left unconnected, VSS_DAC and VDD_DAC must then be connected to GND. Figure 6-15. Typical VGA implementation VDD_DAC COMP VREF_DAC RSET 143 1% 10nF 2.5V VSS_DAC 100nF 100nF 47uF AGND COL_SEL DCLK HSYNC VSYNC R G B 75 1% DALC112S1 3.3V AGND Issue 1.0 - July 24, 2002 87/111 DESIGN GUIDELINES 6.3.10. USB INTERFACE The STPC integrates a USB host interface with a 2-port Hub. The only external device needed are the ESD protection circuits USBDF01W5 and a USB power supply controller. Figure 6-16 describes a typical implementation using these devices. Figure 6-16. Typical USB implementation Connector USBDF02W5(Note1) R = 15 Ohm1 3 1 4 5 2Ohm1 R = 15 1 2 3 4 9 10 USBDMNS[0] USBDPLS[0] USBDMNS[1] USBDPLS[1] USBDF02W5(Note1) R = 15 Ohm1 3 1 4 5 5 6 7 8 GND 11 12 R = 152Ohm1 5V 5V 5V OC 2,3 5 6,7,8 USBVCC TPS2014 POWERON 4 1 100nF 100nF 2x 47uF STPC TPS2014 Power Decoupling Note 1; The ESD protection will be adequate for most applications. In some instances, problems may occur if the devices on the USB chain do not have enough power to drive the signals adequately. We therefore recommend that you replace the part with descrete components and reduce the value of the capacitor. 88/111 Issue 1.0 - July 24, 2002 DESIGN GUIDELINES 6.3.11. KEYBOARD/MOUSE INTERFACE The STPC integrates a PC/AT+ keyboard and PS/2 mouse controller. The only external devices needed are the ESD protection circuits KBMF01SC6. Figure 6-17 describes a typical implementation using a dual minidin connector. Figure 6-17. Typical Keyboard / Mouse implementation 5V 5V MiniDIN MDATA MCLK KBMF01SC6 10 4 14 13 2 6 3 7 8 5V 11 9 15 12 KBDATA KBCLK KBMF01SC6 1 5 16 17 STPC GND Issue 1.0 - July 24, 2002 89/111 DESIGN GUIDELINES 6.3.12. PARALLEL PORT INTERFACE The STPC integrates a parallel port where the only external device needed is the ESD protection Figure 6-18. Typical parallel port implementation circuits ST1284-01A8. Figure 6-18 describes a typical implementation using this device. Connector ACK# BUSY PE SLCT SLCTIN# INIT# ERR# AUTOFD# STROBE# PD[7:0] ST1284-01A8 8 5V 8 STPC 90/111 Issue 1.0 - July 24, 2002 DESIGN GUIDELINES 6.3.13. JTAG INTERFACE The STPC integrates a JTAG interface for scanchain and on-board testing. The only external Figure 6-19. Typical JTAG implementation device needed are the pull up resistors. Figure 619 describes a typical implementation using these devices. 3V3 3V3 3V3 3V3 Connector 10 9 TCLK 8 7 TDO 6 5 TMS TDI 4 3 2 1 TRST STPC Issue 1.0 - July 24, 2002 91/111 DESIGN GUIDELINES 6.4. PLACE AND ROUTE RECOMMENDATIONS All clock signals have to be routed first and shielded for speeds of 27MHz or higher. The high speed signals follow the same constraints, as for the memory and PCI control signals. The next interfaces to be routed are Memory, PCI, and Video/graphics. All the analog noise-sensitive signals have to be routed in a separate area and hence can be routed indepedently. Figure 6-20. Shielding signals 6.4.1. GENERAL RECOMMENDATIONS Some STPC Interfaces run at high speed and need to be carefully routed or even shielded like: 1) Memory Interface 2) PCI bus 3) Graphics and video interfaces 4) 14 MHz oscillator stage ground ring shielded signal line ground pad ground pad shielded signal lines 6.4.2. PLL DEFINITION AND IMPLIMENTATION PLLs are analog cells which supply the internal STPC Clocks. To get the cleanest clock, the jitter on the power supply must be reduced as much as possible. This will result in a more stable system. Each of the integrated PLL has a dedicated power pin so a single power plane for all of these PLLs, or one wire for each, or any solution in between which help the layout of the board can be used. Powering these pins with one Ferrite + capacitances is enough. We recommend at least 2 capacitances: one 'big' (few uF) for power storage, and one or 2 smalls (100nF + 1nF) for noise filtering. 92/111 Issue 1.0 - July 24, 2002 DESIGN GUIDELINES 6.4.3. MEMORY INTERFACE 6.4.3.1. Introduction 6.4.3.2. SDRAM Clocking Scheme In order to achieve SDRAM memory interfaces which work at clock frequencies of 90 MHz and above, careful consideration has to be given to the timing of the interface with all the various electrical and physical constraints taken into consideration. The guidelines described below are related to SDRAM components on DIMM modules. For applications where the memories are directly soldered to the motherboard, the PCB should be laid out such that the trace lengths fit within the constraints shown here. The traces could be slightly shorter since the extra routing on the The SDRAM Clocking Scheme deserves a special mention here. Basically the memory clock is generated on-chip through a PLL and goes directly to the MCLKO output pin of the STPC. The nominal frequency is 90 MHz. Because of the high load presented to the MCLK on the board by the DIMMs it is recommended to rebuffer the MCLKO signal on the board and balance the skew to the clock ports of the different DIMMs and the MCLKI input pin of STPC. DIMM PCB is no longer present but it is then up to the user to verify the timings. Figure 6-21. Clock Scheme MCLKO PLL MCLKI DIMM2 DIMM1 PLL MA[ ] + Control register SDRAM CONTROLLER MD[63:0] 6.4.3.3. Board Layout Issues The physical layout of the motherboard PCB assumed in this presentation is as shown in Figure 6-22. Because all of the memory interface signal balls are located in the same region of the STPC device, it is possible to orientate the device to reduce the trace lengths. The worst case routing length to the DIMM1 is estimated to be 100 mm. Solid power and ground planes are a must in order to provide good return paths for the signals and to reduce EMI and noise. Also there should be ample high frequency decoupling between the power and ground planes to provide a low impedance path between the planes for the return paths for signal routings which change layers. If possible, the traces should be routed adjacent to the same power or ground plane for the length of the trace. For the SDRAM interface, the most critical signal is the clock. Any skew between the clocks at the SDRAM components and the memory controller will impact the timing budget. In order to get well matched clocks at all components it is recommended that all the DIMM clock pins, STPC Issue 1.0 - July 24, 2002 93/111 DESIGN GUIDELINES Figure 6-22. DIMM placement 35mm STPC SDRAM I/F 35mm 15mm DIMM2 10mm DIMM1 116mm memory clock input (MCLKI) and any other component using the memory clock are individually driven from a low skew clock driver with matched routing lengths. In other words, all clock line lengths that go from the buffer to the memory chips (MCLKx) and from the buffer to the STPC (MCLKI) must be identical. This is shown in Figure 6-23. Figure 6-23. Clock Routing Low skew clock driver: L DIMM CKn input DIMM CKn input MCLKO DIMM CKn input L+75mm* STPC MCLKI 20pF * No additional 75mm when SDRAM directly soldered on board 94/111 Issue 1.0 - July 24, 2002 DESIGN GUIDELINES The maximum skew between pins for this part is 250ps. The important factors for the clock buffer are a consistent drive strength and low skew between the outputs. The delay through the buffer is not important so it does not have to be a zero delay PLL type buffer. The trace lengths from the clock driver to the DIMM CKn pins should be matched exactly. Since the propagation speed can vary between PCB layers, the clocks should be routed in a consistent way. The routing to the STPC memory input should be longer by 75 mm to compensate for the extra clock routing on the DIMM. Also a 20 pF capacitor should be placed as near as possible to the clock input of the STPC to compensate for the DIMM's higher clock load. The impedance of the trace used for the clock routing should be matched to the DIMM clock trace impedance (60-75 ohms).To minimise crosstalk the clocks should be routed with spacing to adjacent tracks of at least twice the clock trace width. For designs which use SDRAMs directly mounted on the motherboard PCB all the clock trace lengths should be matched exactly. The DIMM sockets should be populated starting with the furthest DIMM from the STPC device first (DIMM1). There are two types of DIMM devices; single-row and dual-row. The dual-row devices require two chip select signals to select between the two rows. A STPC device with 4 chip select control lines could control either 4 single-row DIMMs or 2 dual-row DIMMs. When only 2 chip select control lines are activated, only two singlerow DIMMs or one dual-row DIMM can be controlled. 6.4.3.4. Summary For unbuffered DIMMs the address/control signals will be the most critical for timing. The simulations show that for these signals the best way to drive them is to use a parallel termination. For applications where speed is not so critical series termination can be used as this will save power. Using a low impedance such as 50 for these critical traces is recommended as it both reduces the delay and the overshoot. The other memory interface signals will typically be not as critical as the address/control signals. Using lower impedance traces is also beneficial for the other signals but if their timing is not as critical as the address/control signals they could use the default value. Using a lower impedance implies using wider traces which may have an impact on the routing of the board. The layout of this interface can be validated by an electrical simulation using the IBIS model available on the STPC web site. 6.4.3.5. Clock topology for on-board SDRAM Figure 6-24 and Figure 6-25 give the recommended clock topology and the resulting IBIS simulation in the case of four on-board SDRAM devices and no clock buffer. Figure 6-24. Recommended topology for 4 on-board SDRAMs (IBIS model) MCLKO 18 Ohms MCLKI 400 mils 400 mils 3500 mils MCLK0 3500 mils MCLK1 Track impedance= 75 Ohms Trace thickness = 0.72 mil Trace width = 4 to 8 mils 3500 mils MCLK2 3500 mils MCLK3 6.4.3.6. Clock topology for standard DIMM Figure 6-26 and Figure 6-27 give the recommend- ed clock topology and the resulting IBIS simulation in the case of a standard DIMM with the use of a clock buffer. Issue 1.0 - July 24, 2002 95/111 DESIGN GUIDELINES Figure 6-25. IBIS Simulation for on-board SDRAM / 90MHz (V) MCLKI 3 MCLKI MCLKx 2 833ps 2.0 V 1 0.8 V 791ps Time Figure 6-26. Recommended topology for DIMM (IBIS model) 22 Ohms Buffer out 3000 mils MCLKI 18 Ohms Buffer out 2000 mils DIMM Track impedance= 75 Ohms Trace thickness = 0.72 mil Trace width = 4 to 8 mils 96/111 Issue 1.0 - July 24, 2002 DESIGN GUIDELINES Figure 6-27. IBIS Simulation for DIMM / 90MHz (V) MCLKx 3 MCLKI Buffer output 2 2.0 V 1.40 ns 1 0.8 V 1.20 ns Time Issue 1.0 - July 24, 2002 97/111 DESIGN GUIDELINES 6.4.4. PCI INTERFACE 6.4.4.1. Introduction In order to achieve a PCI interface which work at clock frequencies up to 33MHz, careful consideration has to be given to the timing of the interface with all the various electrical and physical constraints taken into consideration. 6.4.4.2. PCI Clocking Scheme The PCI Clocking Scheme deserves a special mention here. Basically the PCI clock (PCICLKO) is generated on-chip from HCLK through a programmable delay line and a clock divider. The nominal frequency is 33MHz. This clock must be looped to PCICLKI and goes to the internal South Bridge through a deskewer. On the contrary, the internal North Bridge is clocked by HCLK, putting some additionnal constraints on T0 and T1. Figure 6-28. Clock Scheme HCLK PLL HCLK T0 clock delay MD[30:27] 1/2 1/3 1/4 MD[17,4] PCICLKO T2 T1 PCICLKI Strap Options MD[7:6] Deskewer South Bridge MUX AD[31:0] North Bridge STPC 98/111 Issue 1.0 - July 24, 2002 DESIGN GUIDELINES 6.4.4.3. Board Layout Issues The physical layout of the motherboard PCB assumed in this presentation is as shown in Figure 6-29. For the PCI interface, the most critical signal is the clock. Any skew between the clocks at the PCI components and the STPC will impact the timing budget. In order to get well matched clocks at all components it is recommended that all the PCI clocks are individually driven from a serial resistance with matched routing lengths. In other words, all clock line lengths that go from the resistor to the PCI chips (PCICLKx) must be identical. The figure below is for PCI devices soldered onboard. In the case of a PCI slot, the wire length must be shortened by 2.5" to compensate the clock layout on the PCI board. The maximum clock skew between all devices is 2ns according to PCI specifications. Figure 6-29. Typical PCI clock routing Length(PCICLKI) = Length(PCICLKx) with x = {A,B,C} PCICLKI PCICLKA PCICLKB PCICLKO PCICLKC Device A Device B Device C Note: The value of 22 Ohms corresponds to tracks with Z0 = 70 Ohms. The Figure 6-30 describes a typical clock delay implementation. The exact timing constraints are listed in the PCI section of the Electrical Specifications Chapter. Figure 6-30. Clocks relationships HCLK PCICLKO PCICLKI PCICLKx Issue 1.0 - July 24, 2002 99/111 DESIGN GUIDELINES 6.4.5. THERMAL DISSIPATION 6.4.5.1. Power saving Thermal dissipation of the STPC depends mainly on supply voltage. When the system does not need to work at the upper voltage limit, it may therefore be beneficial to reduce the voltage to the lower voltage limit, where possible. This could save a few 100's of mW. The second area to look at is unused interfaces and functions. Depending on the application, some input signals can be grounded, and some blocks not powered or shutdown. Clock speed dynamic adjustment is also a solution that can be used along with the integrated power management unit. With such configuration the Plastic BGA package does 90% of the thermal dissipation through the ground balls, and especially the central thermal balls which are directly connected to the die. The remaining 10% is dissipated through the case. Adding a heat sink reduces this value to 85%. As a result, some basic rules must be followed when routing the STPC in order to avoid thermal problems. As the whole ground layer acts as a heat sink, the ground balls must be directly connected to it, as illustrated in Figure 6-31. If one ground layer is not enough, a second ground plane may be added. When possible, it is important to avoid other devices on-board using the PCB for heat dissipation, like linear regulators, as this would heat the STPC itself and reduce the temperature range of the whole system, In case these devices can not use a separate heat sink, they must not be located just near the STPC 6.4.5.2. Thermal balls The standard way to route thermal balls to ground layer implements only one via pad for each ball pad, connected using a 8-mil wire. Figure 6-31. Ground Routing Pad for ground ball Thru hole to ground layer To pL aye r: S ign als Po we r la yer Inte rna l La yer :S ign Bo als tto mL aye r: G rou nd lay er 100/111 Issue 1.0 - July 24, 2002 DESIGN GUIDELINES When considering thermal dissipation, one of the most important parts of the layout is the connection between the ground balls and the ground layer. A 1-wire connection is shown in Figure 6-32. The use of a 8-mil wire results in a thermal resistance of 105C/W assuming copper is used (418 W/ m.K). This high value is due to the thickness (34 m) of the copper on the external side of the PCB. Figure 6-32. Recommended 1-wire Power/Ground Pad Layout Pad for ground ball (diameter = 25 mil) Solder Mask (4 mil) Connection Wire (width = 12.5 mil) Via (diameter = 24 mil) Hole to ground layer (diameter = 12 mil) .5 34 Considering only the central matrix of 36 thermal balls and one via for each ball, the global thermal resistance is 2.9C/W. This can be easily improved using four 12.5 mil wires to connect to The use of a ground plane like in Figure 6-34 is even better. il m 1 mil = 0.0254 mm the four vias around the ground pad link as in Figure 6-33. This gives a total of 49 vias and a global resistance for the 36 thermal balls of 0.5C/ W. Figure 6-33. Recommended 4-wire Ground Pad Layout 4 via pads for each ground ball Issue 1.0 - July 24, 2002 101/111 DESIGN GUIDELINES To avoid solder wicking over to the via pads during soldering, it is important to have a solder mask of 4 mil around the pad (NSMD pad). This gives a diameter of 33 mil for a 25 mil ground pad. To obtain the optimum ground layout, place the vias directly under the ball pads. In this case no local board distortion is tolerated. Figure 6-34. Optimum Layout for Central Ground Ball - top layer Clearance = 6mil External diameter = 37 mil Via to Ground layer hole diameter = 14 mil Solder mask diameter = 33 mil Pad for ground ball diameter = 25 mil connections = 10 mil 6.4.5.3. Heat dissipation The thickness of the copper on PCB layers is typically 34 m for external layers and 17 m for internal layers. This means that thermal dissipation is not good; high board temperatures are concentrated around the devices and these fall quickly with increased distance. Where possible, place a metal layer inside the PCB; this improves dramatically the spread of heat and hence the thermal dissipation of the board. The possibility of using the whole system box for thermal dissipation is very useful in cases of high internal temperatures and low outside temperatures. Bottom side of the PBGA should be thermally connected to the metal chassis in order to propagate the heat flow through the metal. Thermally connecting also the top side will improve furthermore the heat dissipation. Figure 6-35 illustrates such an implementation. Figure 6-35. Use of Metal Plate for Thermal Dissipation Die Board Metal planes Thermal conductor 102/111 Issue 1.0 - July 24, 2002 DESIGN GUIDELINES As the PCB acts as a heat sink, the layout of top and ground layers must be done with care to maximize the board surface dissipating the heat. The only limitation is the risk of losing routing channels. Figure 6-36 and Figure 6-37 show a routing with a good thermal dissipation thanks to an optimized placement of power and signal vias. The ground plane should be on bottom layer for the best heat spreading (thicker layer than internal ones) and dissipation (direct contact with air). . Figure 6-36. Layout for Good Thermal Dissipation - top layer 1 A STPC ball Via Not Connected ball GND ball 3.3V ball 2.5V ball (Core / PLLs) Issue 1.0 - July 24, 2002 103/111 DESIGN GUIDELINES Figure 6-37. Recommend signal wiring (top & ground layers) with corresponding heat flow GND Power GND Power Power/GND balls Internal row Signal balls External row Keep-Out = 6 mils Power/GND balls Signal balls 104/111 Issue 1.0 - July 24, 2002 DESIGN GUIDELINES 6.5. DEBUG METHODOLOGY In order to bring a STPC-based board to life with the best efficiency, it is recommended to follow the check-list described in this section. CPU clock mode, this clock must be limited to 66MHz. PCI_CLKI and PCI_CLKO must be connected as described in Figure 6-19 and not be higher than 33MHz. Their speed depends on HCLK and on the divider ratio defined by the MD[4] and MD[17] strap options as described in Section 3. To ensure a correct behaviour of the device, the PCI deskewing logic must be configured properly by the MD[7:6] strap options according to Section 3. For timings constraints, refers to Section 4. 1) MCLKI and MCLKO must be connected as described in Figure 6-3 to Figure 6-5 depending on the SDRAM implementation. The memory clock must run at HCLK speed when in synchronous mode and must not be higher than 90MHz in any case. The MCLK interface will run 100MHz operation is possible but board layout is so critical that 90MHz maximum operation is recommended. 6.5.1. POWER SUPPLIES In parallel with the assembly process, it is useful to get a bare PCB to check the potential shortcircuits between the various power and ground planes. This test is also recommended when the first boards are back from assembly. This will avoid bad surprises in case of a short-circuit due to a bad soldering. When the system is powered, all power supplies, including the PLL power pins must be checked to be sure the right level is present. See Table 4-2 for the exact supported voltage range: VDD_CORE: 2.5V VDD_xxxPLL: 2.5V VDD: 3.3V 6.5.2.4. Reset output If SYSRSTI# and all clocks are correct, then the SYSRSTO# output signal should behave as described in Figure 4-3. 6.5.2. BOOT SEQUENCE 6.5.2.1. Reset input The checking of the reset sequence is the next step. The waveform of SYSRSTI# must complies with the timings described in Figure 4-3. This signal must not have glitches and must stay low until the 14.31818MHz output (OSC14M) is at the right frequency and the strap options are stabilized to a valid configuration. In case this clock is not present, check the 14MHz oscillator stage (see Figure 6-3). 6.5.3. ISA MODE Prior to check the ISA bus control signals, PCI_CLKI, ISA_CLK, ISA_CLK2X, and DEV_CLK must be running properly. If it is not the case, it is probably because one of the previous steps has not been completed. 6.5.3.1. First code fetches When booting on the ISA bus, the two key signals to check at the very beginning are RMRTCCS# and FRAME#. The first one is a Chip Select for the boot flash and is multiplexed with the IDE interface. It should toggle together with ISAOE# and MEMRD# to fetch the first 16 bytes of code. This corresponds to the loading of the first line of the CPU cache. In case RMRTCCS# does not toggle, it is then necessary to check the PCI FRAME# signal. Indeed the ISA controller is part of the South Bridge and all ISA bus cycles are visible on the PCI bus. If there is no activity on the PCI bus, then one of the previous steps has not been checked properly. If there is activity then there must be something conflicting on the ISA bus or on the PCI bus. 6.5.2.2. Strap options The STPC has been designed in a way to allow configurations for test purpose that differs from the functional configuration. In many cases, the troubleshootings at this stage of the debug are the resulting of bad strap options. This is why it is mandatory to check they are properly setup and sampled during the boot sequence. The list of all the strap options is summarized at the beginning of Section 3. 6.5.2.3. Clocks Once OSC14M is checked and correct, the next signals to measure are the Host clock (HCLK), PCI clocks (PCI_CLKO, PCI_CLKI) and Memory clock (MCLKO, MCLKI). HCLK must run at the speed defined by the corresponding strap options (see Table 3-1). In x2 Issue 1.0 - July 24, 2002 105/111 DESIGN GUIDELINES 6.5.3.2. Boot Flash size The ISA bus supports 8-bit and 16-bit memory devices. In case of a 16-bit boot flash, the signal MEMCS16# must be activated during RMRTCCS# cycle to inform the ISA controller of a 16-bit device. toggle together with PRD# to fetch the first 16 bytes of code. This corresponds to the loading of the first line of the CPU cache. In case FCS0# does not toggle, then one of the previous steps has not been done properly, like HCLK speed and CPU clock multiplier (x1, x2). 6.5.4.2. Boot Flash size 6.5.3.3. POST code Once the 16 first bytes are fetched and decoded, the CPU core continue its execution depending on the content of these first data. Usually, it corresponds to a JUMP instruction and the code fetching continues, generating read cycles on the ISA bus. Most of the BIOS and boot loaders are reading the content of the flash, decompressing it in SDRAM, and then continue the execution by jumping to the entry point in RAM. This boot process ends with a JUMP to the entry point of the OS launcher. These various steps of the booting sequence are codified by the so-called POST codes (Power-On Self-Test). A 8-bit code is written to the port 80H at the beginning of each stage of the booting process (I/O write to address 0080H) and can be displayed on two 7-segment display, enabling a fast visual check of the booting completion level. Usually, the last POST code is 0x00 and corresponds to the jump into the OS launcher. When the execution fails or hangs, the lastest written code stays visible on that display, indicating either the piece of code to analyse, either the area of the hardware not working properly. The Local Bus support 16-bit boot memory devices only. 6.5.4.3. POST code Like in ISA mode, POST codes can be implemented on the Local Bus. The difference is that an IOCS# must be programmed at I/O address 80H prior to writing these code, the POST display being connected to this IOCS# and to the lower 8 bits of the bus. 6.5.5. SUMMARY Here is a check-list for the STPC board debug from power-on to CPU execution. For each step, in case of failure, verify first the corresponding balls of the STPC: - check if the voltage or activity is correct - search for potential shortcuts. For troubleshooting in steps 5 to 10, verify the related strap options: - value & connection. Refer to Section 3. - see Figure 4-3 for timing constraints Steps 8a and 9a are for debug in ISA mode while steps 8b and 9b are for Local Bus mode. 6.5.4. LOCAL BUS MODE As the Local Bus controller is located into the Host interface, there is no access to the cycles on the PCI, reducing the amount of signals to check. 6.5.4.1. First code fetches When booting on the Local Bus, the key signal to check at the very beginning is FCS0#. This signal is a Chip Select for the boot flash and should Check: How? Verify that voltage is within specs: - this must include HF & LF noise - avoid full range sweep Refer to Table 4-1 for values 6.5.6. PCMCIA MODE As the STPC uses the RMRTCCS# signal for booting in that mode, the methodology is the same as for the ISA bus. The PCMCIA cards being 3.3V or 5V, the boot flash device must be 5V tolerant when directly connected on the address and data busses. An other solution is to isolate the flash from the PCMCIA lines using 5V tolerant LVTTL buffers. Troubleshooting Measure voltage near STPC balls: - use very low GND connection. Add some decoupling capacitor: - the smallest, the nearest to STPC balls. The 2 capacitors used with the quartz must match with the capacitance of the crystal. Try other values. 1 Power supplies 2 14.318 MHz Verify OSC14M speed 106/111 Issue 1.0 - July 24, 2002 DESIGN GUIDELINES Check: SYSRSTI# (Power Good) How? Measure SYSRSTI# of STPC See Figure 4-3 for waveforms. Measure HCLK is at selected frequency 25MHz < HCLK < 66MHz Measure PCICLKO: - maximum is 33MHz by standard - check it is at selected frequency - it is generated from HCLK by a division (1/2, 1/3 or 1/4) Check PCICLKI equals PCICLKO Measure MCLKO: - use a low-capacitance probe - maximum is 90MHz - check it is at selected frequency - In SYNC mode MCLK=HCLK - in ASYNC mode, default is 66MHz Check MCLKI equals MCLKO Measure SYSRSTO# of STPC See Figure 4-3 for waveforms. Check PCI signals are toggling: - FRAME#, IRDY#, TRDY#, DEVSEL# - these signals are active low. Check, with a logic analyzer, that first PCI cycles are the expected ones: memory read starting at address with lower bits to 0xFFF0 Troubleshooting Verify reset generation circuit: - device reference - components value HCLK wire must be as short as possible 3 5 HCLK 6 PCI clocks Verify PCICLKO loops to PCICLKI. Verify maximum skew between any PCI clock branch is below 2ns. In Synchronous mode, check MCLKI. 7 Memory clocks Verify load on MCLKI. Verify MCLK programming (BIOS setting). 4 SYSRSTO# Verify SYSRSTI# duration. Verify SYSRSTI# has no glitch Verify clocks are running. 8a PCI cycles Verify PCI slots If the STPC don't boot - verify data read from boot memory is OK - ensure Flash is correctly programmed - ensure CMOS is cleared. 9a ISA cycles to boot memory Check RMRTCCS# & MEMRD# Check directly on boot memory pin Verify MEMCS16#: - must not be asserted for 8-bit memory Verify IOCHRDY is not be asserted Verify ISAOE# pin: - it controls IDE / ISA bus demultiplexing Verify HCLK speed and CPU clock mode. If the STPC don't boot - verify data read from boot memory is OK - ensure Flash is correctly programmed - ensure CMOS is cleared. 8b Local Bus cycles to boot memory Check FCS0# & PRD# Check directly on boot memory pin Check, with a logic analyzer, that first Local Bus cycles are the expected one: memory read starting at the top of boot memory less 16 bytes 9b The CPU fills its first cache line by fetching 16 bytes from boot memory. Then, first instructions are executed from the CPU. 10 Any boot memory access done after the first 16 bytes are due to the instructions executed by the CPU => Minimum hardware is correctly set, CPU executes code. Please have a look to the Bios Writer's Guide or Programming Manual to go further with your board testing. Issue 1.0 - July 24, 2002 107/111 DESIGN GUIDELINES 6.5.7. 108/111 Issue 1.0 - July 24, 2002 ORDERING DATA 7. ORDERING DATA 7.1. ORDERING CODES ST STMicroelectronics Prefix Product Family PC: PC Compatible Product ID I2: Atlas Core Speed G: 120 MHz H: 133 MHz Memory Speed D: 90 MHz E: 100 MHz Package Y: 516 Overmoulded BGA Temperature Range C: Commercial Tcase = 0 to +85C I: Industrial Tcase = -40 to +115C PC I2 H E Y C Issue 1.0 - July 24, 2002 109/111 ORDERING DATA 7.2. AVAILABLE PART NUMBERS Part Number STPCI2HEYC1 Core Frequency (MHz) 133 CPU Mode X2 Memory Interface Speed (MHz) 90 Tcase Range (C) 0C to +85C Operating Voltage (V) 2.45 - 2.7 STPCI2GDYI 120 X2 90 -40C to +115C 3.0 - 3.6 Note 1: The STPC Atlas MClock signal can run up to 100MHz reliably, but PCB layout is so critical that the maximum guaranteed speed is 90MHz 110/111 Issue 1.0 - July 24, 2002 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) 2000 STMicroelectronics - All Rights Reserved The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 111 Issue 1.0 |
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